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<dblpperson name="Victor V. Zhirnov" pid="20/201" n="14">
<person key="homepages/20/201" mdate="2009-06-08">
<author pid="20/201">Victor V. Zhirnov</author>
</person>
<r><proceedings key="conf/glvlsi/2021" mdate="2022-07-04">
<editor pid="80/1641">Yiran Chen 0001</editor>
<editor pid="20/201">Victor V. Zhirnov</editor>
<editor pid="83/7356">Avesta Sasan</editor>
<editor pid="37/3387">Ioannis Savidis</editor>
<title>GLSVLSI '21: Great Lakes Symposium on VLSI 2021, Virtual Event, USA, June 22-25, 2021.</title>
<publisher>ACM</publisher>
<booktitle>ACM Great Lakes Symposium on VLSI</booktitle>
<year>2021</year>
<isbn>978-1-4503-8393-6</isbn>
<ee>https://doi.org/10.1145/3453688</ee>
<url>db/conf/glvlsi/glvlsi2021.html</url>
</proceedings>
</r>
<r><article key="journals/pieee/MakkiZCII18" mdate="2025-01-19">
<author pid="03/5157">Rafic Z. Makki</author>
<author pid="20/201">Victor V. Zhirnov</author>
<author orcid="0000-0002-5810-5660" pid="15/240">Ralph K. Cavin III</author>
<author pid="78/666">Sami Issa</author>
<author pid="59/5427">Marco Iansiti</author>
<title>Nurturing the Growth of a National Infrastructure in Emerging Technologies.</title>
<pages>1126-1131</pages>
<year>2018</year>
<volume>106</volume>
<journal>Proc. IEEE</journal>
<number>7</number>
<ee>https://doi.org/10.1109/JPROC.2018.2838638</ee>
<ee>https://www.wikidata.org/entity/Q129459886</ee>
<url>db/journals/pieee/pieee106.html#MakkiZCII18</url>
</article>
</r>
<r><article key="journals/pieee/CavinLZ12" mdate="2020-10-02">
<author pid="15/240">Ralph K. Cavin III</author>
<author pid="01/4670">Paolo Lugli</author>
<author pid="20/201">Victor V. Zhirnov</author>
<title>Prolog to the Section on Science and Engineering Beyond Moore's Law.</title>
<pages>1718-1719</pages>
<year>2012</year>
<volume>100</volume>
<journal>Proc. IEEE</journal>
<number>Centennial-Issue</number>
<ee type="oa">https://doi.org/10.1109/JPROC.2012.2189807</ee>
<url>db/journals/pieee/pieee100.html#CavinLZ12</url>
</article>
</r>
<r><article key="journals/pieee/CavinLZ12a" mdate="2020-10-02">
<author pid="15/240">Ralph K. Cavin III</author>
<author pid="01/4670">Paolo Lugli</author>
<author pid="20/201">Victor V. Zhirnov</author>
<title>Science and Engineering Beyond Moore's Law.</title>
<pages>1720-1749</pages>
<year>2012</year>
<volume>100</volume>
<journal>Proc. IEEE</journal>
<number>Centennial-Issue</number>
<ee type="oa">https://doi.org/10.1109/JPROC.2012.2190155</ee>
<ee>https://www.wikidata.org/entity/Q56070055</ee>
<url>db/journals/pieee/pieee100.html#CavinLZ12a</url>
</article>
</r>
<r><article key="journals/pieee/ZhirnovCMLSBSW10" mdate="2020-10-02">
<author pid="20/201">Victor V. Zhirnov</author>
<author pid="15/240">Ralph K. Cavin III</author>
<author orcid="0000-0002-4258-2673" pid="119/4093">Stephan Menzel</author>
<author pid="122/4173">Eike Linn</author>
<author pid="57/10647">Sebastian Schmelzer</author>
<author pid="122/4132">Dennis Br&#228;uhaus</author>
<author orcid="0000-0002-5345-6293" pid="122/4137">Christina Schindler</author>
<author orcid="0000-0002-9080-8980" pid="31/3874">Rainer Waser</author>
<title>Memory Devices: Energy-Space-Time Tradeoffs.</title>
<pages>2185-2200</pages>
<year>2010</year>
<volume>98</volume>
<journal>Proc. IEEE</journal>
<number>12</number>
<ee>https://doi.org/10.1109/JPROC.2010.2064271</ee>
<url>db/journals/pieee/pieee98.html#ZhirnovCMLSBSW10</url>
</article>
</r>
<r><inproceedings key="conf/esscirc/ZhirnovC09" mdate="2020-07-07">
<author pid="20/201">Victor V. Zhirnov</author>
<author pid="15/240">Ralph K. Cavin III</author>
<title>Scaling beyond CMOS: Turing-Heisenberg Rapproachment.</title>
<pages>16-22</pages>
<year>2009</year>
<booktitle>ESSCIRC</booktitle>
<ee>https://doi.org/10.1109/ESSCIRC.2009.5325930</ee>
<crossref>conf/esscirc/2009</crossref>
<url>db/conf/esscirc/esscirc2009.html#ZhirnovC09</url>
</inproceedings>
</r>
<r><article key="journals/computer/ZhirnovCLG08" mdate="2020-08-12">
<author pid="20/201">Victor V. Zhirnov</author>
<author pid="15/240">Ralph K. Cavin III</author>
<author pid="31/4204">Greg Leeming</author>
<author pid="67/4147">Kosmas Galatsis</author>
<title>An Assessment of Integrated Digital Cellular Automata Architectures.</title>
<pages>38-44</pages>
<year>2008</year>
<volume>41</volume>
<journal>Computer</journal>
<number>1</number>
<ee>https://doi.org/10.1109/MC.2008.4</ee>
<ee>http://doi.ieeecomputersociety.org/10.1109/MC.2008.4</ee>
<url>db/journals/computer/computer41.html#ZhirnovCLG08</url>
</article>
</r>
<r><article key="journals/computer/HutchbyCZBB08" mdate="2020-08-12">
<author pid="69/5831">James A. Hutchby</author>
<author pid="15/240">Ralph K. Cavin III</author>
<author pid="20/201">Victor V. Zhirnov</author>
<author pid="48/2566">Joe E. Brewer</author>
<author pid="01/6067">George Bourianoff</author>
<title>Emerging Nanoscale Memory and Logic Devices: A Critical Assessment.</title>
<pages>28-32</pages>
<year>2008</year>
<volume>41</volume>
<journal>Computer</journal>
<number>5</number>
<ee>https://doi.org/10.1109/MC.2008.154</ee>
<ee>http://doi.ieeecomputersociety.org/10.1109/MC.2008.154</ee>
<url>db/journals/computer/computer41.html#HutchbyCZBB08</url>
</article>
</r>
<r><article key="journals/computer/CavinHZBB08" mdate="2020-08-12">
<author pid="15/240">Ralph K. Cavin III</author>
<author pid="69/5831">James A. Hutchby</author>
<author pid="20/201">Victor V. Zhirnov</author>
<author pid="48/2566">Joe E. Brewer</author>
<author pid="01/6067">George Bourianoff</author>
<title>Emerging Research Architectures.</title>
<pages>33-37</pages>
<year>2008</year>
<volume>41</volume>
<journal>Computer</journal>
<number>5</number>
<ee>https://doi.org/10.1109/MC.2008.155</ee>
<ee>http://doi.ieeecomputersociety.org/10.1109/MC.2008.155</ee>
<url>db/journals/computer/computer41.html#CavinHZBB08</url>
</article>
</r>
<r><article key="journals/computer/BourianoffBCHZ08" mdate="2020-08-12">
<author pid="01/6067">George Bourianoff</author>
<author pid="48/2566">Joe E. Brewer</author>
<author pid="15/240">Ralph K. Cavin III</author>
<author pid="69/5831">James A. Hutchby</author>
<author pid="20/201">Victor V. Zhirnov</author>
<title>Boolean Logic and Alternative Information-Processing Devices.</title>
<pages>38-46</pages>
<year>2008</year>
<volume>41</volume>
<journal>Computer</journal>
<number>5</number>
<ee>https://doi.org/10.1109/MC.2008.145</ee>
<ee>http://doi.ieeecomputersociety.org/10.1109/MC.2008.145</ee>
<url>db/journals/computer/computer41.html#BourianoffBCHZ08</url>
</article>
</r>
<r><inproceedings key="conf/ersa/ZhirnovLGC08" mdate="2009-02-12">
<author pid="20/201">Victor V. Zhirnov</author>
<author pid="31/4204">Greg Leeming</author>
<author pid="67/4147">Kosmas Galatsis</author>
<author pid="15/240">Ralph K. Cavin III</author>
<title>The Viability of Cellular Automata Architectures for General Purpose Computing.</title>
<pages>321-333</pages>
<year>2008</year>
<booktitle>ERSA</booktitle>
<crossref>conf/ersa/2008</crossref>
<url>db/conf/ersa/ersa2008.html#ZhirnovLGC08</url>
</inproceedings>
</r>
<r><inproceedings key="conf/esscirc/CavinZ05" mdate="2023-04-28">
<author pid="15/240">Ralph K. Cavin III</author>
<author pid="20/201">Victor V. Zhirnov</author>
<title>Future devices for information processing.</title>
<pages>7-12</pages>
<year>2005</year>
<booktitle>ESSCIRC</booktitle>
<ee>https://doi.org/10.1109/ESSCIR.2005.1541550</ee>
<crossref>conf/esscirc/2005</crossref>
<url>db/conf/esscirc/esscirc2005.html#CavinZ05</url>
</inproceedings>
</r>
<r><article key="journals/pieee/ZhirnovCHB03" mdate="2021-08-30">
<author pid="20/201">Victor V. Zhirnov</author>
<author pid="15/240">Ralph K. Cavin III</author>
<author pid="69/5831">James A. Hutchby</author>
<author pid="01/6067">George Bourianoff</author>
<title>Limits to binary logic switch scaling - a gedanken model.</title>
<pages>1934-1939</pages>
<year>2003</year>
<volume>91</volume>
<journal>Proc. IEEE</journal>
<number>11</number>
<ee>https://doi.org/10.1109/JPROC.2003.818324</ee>
<url>db/journals/pieee/pieee91.html#ZhirnovCHB03</url>
</article>
</r>
<r><article key="journals/computer/ZhirnovH01" mdate="2020-08-12">
<author pid="20/201">Victor V. Zhirnov</author>
<author pid="81/3773">Daniel J. C. Herr</author>
<title>New Frontiers: Self-Assembly and Nanoelectronics.</title>
<pages>34-43</pages>
<year>2001</year>
<volume>34</volume>
<journal>Computer</journal>
<number>1</number>
<ee>https://doi.org/10.1109/2.895116</ee>
<ee>http://doi.ieeecomputersociety.org/10.1109/2.895116</ee>
<url>db/journals/computer/computer34.html#ZhirnovH01</url>
</article>
</r>
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<co c="0"><na f="b/Bourianoff:George" pid="01/6067">George Bourianoff</na></co>
<co c="0"><na f="b/Br=auml=uhaus:Dennis" pid="122/4132">Dennis Br&#228;uhaus</na></co>
<co c="0"><na f="b/Brewer:Joe_E=" pid="48/2566">Joe E. Brewer</na></co>
<co c="0"><na f="c/Cavin_III:Ralph_K=" pid="15/240">Ralph K. Cavin III</na></co>
<co c="1"><na f="c/Chen_0001:Yiran" pid="80/1641">Yiran Chen 0001</na></co>
<co c="0"><na f="g/Galatsis:Kosmas" pid="67/4147">Kosmas Galatsis</na></co>
<co c="-1"><na f="h/Herr:Daniel_J=_C=" pid="81/3773">Daniel J. C. Herr</na></co>
<co c="0"><na f="h/Hutchby:James_A=" pid="69/5831">James A. Hutchby</na></co>
<co c="0"><na f="i/Iansiti:Marco" pid="59/5427">Marco Iansiti</na></co>
<co c="0"><na f="i/Issa:Sami" pid="78/666">Sami Issa</na></co>
<co c="0"><na f="l/Leeming:Greg" pid="31/4204">Greg Leeming</na></co>
<co c="0"><na f="l/Linn:Eike" pid="122/4173">Eike Linn</na></co>
<co c="0"><na f="l/Lugli:Paolo" pid="01/4670">Paolo Lugli</na></co>
<co c="0"><na f="m/Makki:Rafic_Z=" pid="03/5157">Rafic Z. Makki</na></co>
<co c="0"><na f="m/Menzel:Stephan" pid="119/4093">Stephan Menzel</na></co>
<co c="1"><na f="s/Sasan:Avesta" pid="83/7356">Avesta Sasan</na></co>
<co c="1"><na f="s/Savidis:Ioannis" pid="37/3387">Ioannis Savidis</na></co>
<co c="0"><na f="s/Schindler:Christina" pid="122/4137">Christina Schindler</na></co>
<co c="0"><na f="s/Schmelzer:Sebastian" pid="57/10647">Sebastian Schmelzer</na></co>
<co c="0"><na f="w/Waser:Rainer" pid="31/3874">Rainer Waser</na></co>
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