New sensing technique for detecting application layer DDoS attacks targeting back-end database resources.

John V. McCanny John Vincent McCanny Queen's University Belfast, UK http://www.ee.qub.ac.uk/staff/academic/jvmcc.htm David Beckett Sakir Sezer John V. McCanny New sensing technique for detecting application layer DDoS attacks targeting back-end database resources. 1-7 2017 ICC https://doi.org/10.1109/ICC.2017.7997376 conf/icc/2017 db/conf/icc/icc2017.html#BeckettSM17 Ye Lu 0003 Changlin Chen John V. McCanny Sakir Sezer Design of interlock-free combined allocators for Networks-on-Chip. 358-363 2012 SoCC https://doi.org/10.1109/SOCC.2012.6398332 conf/socc/2012 db/conf/socc/socc2012.html#LuCMS12

Lei Ma 0012 Kevin Dickson John McAllister John V. McCanny QR Decomposition-Based Matrix Inversion for High Performance Embedded MIMO Receivers. 1858-1867 2011 59 IEEE Trans. Signal Process. 4 https://doi.org/10.1109/TSP.2011.2105485 db/journals/tsp/tsp59.html#MaDMM11

Ye Lu 0003 John V. McCanny Sakir Sezer Generic Low-Latency NoC Router Architecture for FPGA Computing Systems. 82-89 2011 FPL https://doi.org/10.1109/FPL.2011.25 https://doi.ieeecomputersociety.org/10.1109/FPL.2011.25 conf/fpl/2011 db/conf/fpl/fpl2011.html#LuMS11 Ye Lu 0003 John V. McCanny Sakir Sezer The Impact of Global Routing on the Performance of NoCs in FPGAs. 369-374 2011 ReConFig https://doi.org/10.1109/ReConFig.2011.87 https://doi.ieeecomputersociety.org/10.1109/ReConFig.2011.87 conf/reconfig/2011 db/conf/reconfig/reconfig2011.html#LuMS11 Ye Lu 0003 John V. McCanny Sakir Sezer Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip. 302-307 2011 SoCC https://doi.org/10.1109/SOCC.2011.6085089 conf/socc/2011 db/conf/socc/socc2011.html#LuMS11

Liang Lu John V. McCanny Sakir Sezer Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding. 349-364 2010 4 IET Comput. Digit. Tech. 5 https://doi.org/10.1049/iet-cdt.2008.0106 db/journals/iet-cdt/iet-cdt4.html#LuMS10

Yingxi Lu Máire O'Neill John V. McCanny Evaluation of Random Delay Insertion against DPA on FPGAs. 11:1-11:20 2010 4 ACM Trans. Reconfigurable Technol. Syst. 1 https://doi.org/10.1145/1857927.1857938 https://www.wikidata.org/entity/Q130991924 db/journals/trets/trets4.html#LuOM10

Ye Lu 0003 Sakir Sezer John V. McCanny Advanced Multithreading Architecture with Hardware Based Scheduling. 95-100 2010 FPL https://doi.org/10.1109/FPL.2010.28 https://doi.ieeecomputersociety.org/10.1109/FPL.2010.28 conf/fpl/2010 db/conf/fpl/fpl2010.html#LuSM10 Ye Lu 0003 Sakir Sezer John V. McCanny TLM2.0 based timing accurate modeling method for complex NoC systems. 2900-2903 2010 ISCAS https://doi.org/10.1109/ISCAS.2010.5538041 conf/iscas/2010 db/conf/iscas/iscas2010.html#LuSM10 Ye Lu 0003 Sakir Sezer John V. McCanny Design and analysis of an advanced static blocked multithreading architecture. 169-173 2010 SoCC https://doi.org/10.1109/SOCC.2010.5784736 conf/socc/2010 db/conf/socc/socc2010.html#LuSM10 Xin Yang 0010 Sakir Sezer John V. McCanny Dwayne Burns High-Performance random data lookup for network processing. 272-277 2010 SoCC https://doi.org/10.1109/SOCC.2010.5784758 conf/socc/2010 db/conf/socc/socc2010.html#YangSMB10

Liang Lu John V. McCanny Sakir Sezer Subpixel Interpolation Architecture for Multistandard Video Motion Estimation. 1897-1901 2009 19 IEEE Trans. Circuits Syst. Video Technol. 12 https://doi.org/10.1109/TCSVT.2009.2026942 db/journals/tcsv/tcsv19.html#LuMS09

Yingxi Lu Keanhong Boey Máire O'Neill John V. McCanny Akashi Satoh Is the differential frequency-based attack effective against random delay insertion? 051-056 2009 SiPS https://doi.org/10.1109/SIPS.2009.5336291 conf/sips/2009 db/conf/sips/sips2009.html#LuBOMS09 Yongping Liu Sakir Sezer John V. McCanny NFA decomposition and multiprocessing architecture for parallel regular expression processing. 347-350 2009 SoCC https://doi.org/10.1109/SOCCON.2009.5398023 conf/socc/2009 db/conf/socc/socc2009.html#LiuSM09 Xin Yang 0010 Sakir Sezer John V. McCanny Dwayne Burns DDR3 based lookup circuit for high-performance network processing. 351-354 2009 SoCC https://doi.org/10.1109/SOCCON.2009.5398024 conf/socc/2009 db/conf/socc/socc2009.html#YangSMB09

Yen-Kuang Chen David W. Lin John V. McCanny Edwin Hsing-Mean Sha Guest Editorial: Special Issue on Design and Programming of Signal Processors for Multimedia Communication. 207-208 2008 51 J. Signal Process. Syst. 3 https://doi.org/10.1007/s11265-007-0159-1 db/journals/vlsisp/vlsisp51.html#ChenLMS08

Roger F. Woods John V. McCanny John G. McWhirter From Bit Level Systolic Arrays to HDTV Processor Chips. 35-49 2008 53 J. Signal Process. Syst. 1-2 https://doi.org/10.1007/s11265-007-0132-z db/journals/vlsisp/vlsisp53.html#WoodsMM08

Yingxi Lu Máire O'Neill John V. McCanny FPGA implementation and analysis of random delay insertion countermeasure against DPA. 201-208 2008 FPT https://doi.org/10.1109/FPT.2008.4762384 conf/fpt/2008 db/conf/fpt/fpt2008.html#LuOM08 Lei Ma 0012 Kevin Dickson John McAllister John V. McCanny Modified givens rotations and their application to matrix inversion. 1437-1440 2008 ICASSP https://doi.org/10.1109/ICASSP.2008.4517890 conf/icassp/2008 db/conf/icassp/icassp2008.html#MaDMM08 Yingxi Lu Máire O'Neill John V. McCanny Differential Power Analysis of a SHACAL-2 hardware implementation. 2933-2936 2008 ISCAS https://doi.org/10.1109/ISCAS.2008.4542072 conf/iscas/2008 db/conf/iscas/iscas2008.html#LuOM08 Lei Ma 0012 Kevin Dickson John McAllister John V. McCanny Mathini Sellathurai Reduced-complexity MSGR-based matrix inversion. 124-128 2008 SiPS https://doi.org/10.1109/SIPS.2008.4671749 conf/sips/2008 db/conf/sips/sips2008.html#MaDMMS08 Liang Lu John V. McCanny Sakir Sezer Multi-standard sub-pixel interpolation architecture for video Motion Estimation. 229-232 2008 SoCC https://doi.org/10.1109/SOCC.2008.4641517 conf/socc/2008 db/conf/socc/socc2008.html#LuMS08 Xin Yang 0010 Jun Mu Sakir Sezer John V. McCanny Earl E. Swartzlander Jr. High performance IP lookup circuit using DDR SDRAM. 371-374 2008 SoCC https://doi.org/10.1109/SOCC.2008.4641547 conf/socc/2008 db/conf/socc/socc2008.html#YangMSMS08 Liang Lu John V. McCanny Sakir Sezer Systolic Array Based Architecture for Variable Block-Size Motion Estimation. 160-168 2007 AHS https://doi.org/10.1109/AHS.2007.103 https://doi.ieeecomputersociety.org/10.1109/AHS.2007.103 conf/ahs/2007 db/conf/ahs/ahs2007.html#LuMS07 Xin Yang 0010 Sakir Sezer John V. McCanny Dwayne Burns Novel Content Addressable Memory Architecture for Adaptive Systems. 633-640 2007 AHS https://doi.org/10.1109/AHS.2007.79 https://doi.ieeecomputersociety.org/10.1109/AHS.2007.79 conf/ahs/2007 db/conf/ahs/ahs2007.html#YangSMB07 Liang Lu John V. McCanny Sakir Sezer Reconfigurable Motion Estimation Architecture for Multi-standard Video Compression. 253-259 2007 ASAP https://doi.org/10.1109/ASAP.2007.4429989 https://doi.ieeecomputersociety.org/10.1109/ASAP.2007.4429989 conf/asap/2007 db/conf/asap/asap2007.html#LuMS07 John V. McCanny Sakir Sezer Máire O'Neill Exploring technology related design-space limitations of high performance network processing. 222-231 2007 ESSCIRC https://doi.org/10.1109/ESSCIRC.2007.4430285 conf/esscirc/2007 db/conf/esscirc/esscirc2007.html#McCannySO07 John V. McCanny From Special Purpose VLSI Architectures to HDTV Processors and Gigabit Wireless Systems. 16 2007 DSP https://doi.org/10.1109/ICDSP.2007.4288506 conf/icdsp/2007 db/conf/icdsp/icdsp2007.html#McCanny07 Liang Lu John V. McCanny Sakir Sezer Reconfigurable video motion estimation processor. 55-58 2007 SoCC https://doi.org/10.1109/SOCC.2007.4545425 conf/socc/2007 db/conf/socc/socc2007.html#LuMS07 Xin Yang 0010 Sakir Sezer John V. McCanny Dwayne Burns A versatile content addressable memory architecture. 215-218 2007 SoCC https://doi.org/10.1109/SOCC.2007.4545461 conf/socc/2007 db/conf/socc/socc2007.html#YangSMB07

Neil Smyth Máire McLoone John V. McCanny WLAN security processor. 1506-1520 2006 53-I IEEE Trans. Circuits Syst. I Regul. Pap. 7 https://doi.org/10.1109/TCSI.2006.877888 db/journals/tcas/tcasI53.html#SmythMM06

Ciaran McIvor Máire McLoone John V. McCanny Hardware Elliptic Curve Cryptographic Processor Over $\rm GF(p)$. 1946-1957 2006 53-I IEEE Trans. Circuits Syst. I Regul. Pap. 9 https://doi.org/10.1109/TCSI.2006.880184 db/journals/tcas/tcasI53.html#McIvorMM06

Friederich Kupzog Holger Blume Tobias G. Noll Kieran McLaughlin Sakir Sezer John V. McCanny Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup. 56 2006 conf/aict/2006 AICT/ICIW https://doi.org/10.1109/AICT-ICIW.2006.76 https://doi.ieeecomputersociety.org/10.1109/AICT-ICIW.2006.76 db/conf/aict/aict2006.html#KupzogBNMSM06 John V. McCanny Roger F. Woods John G. McWhirter From Bit Level Systolic Arrays to HDTV Processor Chips. 159-162 2006 conf/asap/2006 ASAP https://doi.org/10.1109/ASAP.2006.35 https://doi.ieeecomputersociety.org/10.1109/ASAP.2006.35 db/conf/asap/asap2006.html#McCannyWM06 Neil Smyth Máire McLoone John V. McCanny An Adaptable And Scalable Asymmetric Cryptographic Processor. 341-346 2006 conf/asap/2006 ASAP https://doi.org/10.1109/ASAP.2006.8 https://doi.ieeecomputersociety.org/10.1109/ASAP.2006.8 db/conf/asap/asap2006.html#SmythMM06 Kieran McLaughlin Friederich Kupzog Holger Blume Sakir Sezer Tobias G. Noll John V. McCanny Design and analysis of matching circuit architectures for a closest match lookup. 2006 conf/ipps/2006 IPDPS https://doi.org/10.1109/IPDPS.2006.1639481 https://doi.ieeecomputersociety.org/10.1109/IPDPS.2006.1639481 db/conf/ipps/ipdps2006.html#McLaughlinKBSNM06

Zhaohui Liu Kevin Dickson John V. McCanny Application-specific instruction set processor for SoC implementation of modern signal processing algorithms. 755-765 2005 52-I IEEE Trans. Circuits Syst. I Regul. Pap. 4 https://doi.org/10.1109/TCSI.2005.844109 db/journals/tcas/tcasI52.html#LiuDM05

Ciaran McIvor Máire McLoone John V. McCanny High-Radix Systolic Modular Multiplication on Reconfigurable Hardware. 13-18 2005 conf/fpt/2005 FPT db/conf/fpt/fpt2005.html#McIvorMM05 Zhaohui Liu Kevin Dickson John V. McCanny Hardware Design of Sphere Decoding for MIMO Systems. 287-290 2005 SoCC https://doi.org/10.1109/SOCC.2005.1554512 conf/socc/2005 db/conf/socc/socc2005.html#LiuDM05

Shahid Masud John V. McCanny Reusable silicon IP cores for discrete wavelet transform applications. 1114-1124 2004 51-I IEEE Trans. Circuits Syst. I Regul. Pap. 6 https://doi.org/10.1109/TCSI.2004.829236 db/journals/tcas/tcasI51.html#MasudM04

Swee Yeow Yap John V. McCanny A VLSI architecture for variable block size video motion estimation. 384-389 2004 51-II IEEE Trans. Circuits Syst. II Express Briefs 7 https://doi.org/10.1109/TCSII.2004.829555 db/journals/tcas/tcasII51.html#YapM04

Ciaran McIvor Máire McLoone John V. McCanny FPGA Montgomery Multiplier Architectures - A Comparison. 279-282 2004 conf/fccm/2004 FCCM https://doi.org/10.1109/FCCM.2004.36 https://doi.ieeecomputersociety.org/10.1109/FCCM.2004.36 db/conf/fccm/fccm2004.html#McIvorMM04 Máire McLoone Ciaran McIvor John V. McCanny Coarsely integrated operand scanning (CIOS) architecture for high-speed Montgomery modular multiplication. 185-191 2004 FPT https://doi.org/10.1109/FPT.2004.1393267 conf/fpt/2004 db/conf/fpt/fpt2004.html#McLooneMM04 Ciaran McIvor Máire McLoone John V. McCanny FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p). 509-512 2004 conf/iscas/2004 ISCAS (3) https://doi.org/10.1109/ISCAS.2004.1328795 db/conf/iscas/iscas2004-3.html#McIvorMM04

Zhaohui Liu John V. McCanny Gaye Lightbody Richard L. Walke Generic SoC QR array processor for adaptive beamforming. 169-175 2003 50 IEEE Trans. Circuits Syst. II Express Briefs 4 https://doi.org/10.1109/TCSII.2003.810487 db/journals/tcasII/tcasII50.html#LiuMLW03

Máire McLoone John V. McCanny Rijndael FPGA Implementations Utilising Look-Up Tables. 261-275 2003 34 J. VLSI Signal Process. 3 https://doi.org/10.1023/A:1023252403567 db/journals/vlsisp/vlsisp34.html#McLooneM03

Zhaohui Liu Kevin Dickson John V. McCanny A floating-point CORDIC based SVD processor. 194-203 2003 conf/asap/2003 ASAP https://doi.org/10.1109/ASAP.2003.1212843 https://doi.ieeecomputersociety.org/10.1109/ASAP.2003.1212843 db/conf/asap/asap2003.html#LiuDM03 Swee Yeow Yap John V. McCanny A VLSI Architecture for Advanced Video Coding Motion Estimation. 293- 2003 conf/asap/2003 ASAP https://doi.org/10.1109/ASAP.2003.1212853 https://doi.ieeecomputersociety.org/10.1109/ASAP.2003.1212853 db/conf/asap/asap2003.html#YeowM03 Máire McLoone John V. McCanny Very High Speed 17 Gbps SHACAL Encryption Architecture. 111-120 https://doi.org/10.1007/978-3-540-45234-8_12 2003 conf/fpl/2003 FPL db/conf/fpl/fpl2003.html#McLooneM03 Zhaohui Liu John V. McCanny Implementation of adaptive beamforming based on QR decomposition for CDMA. 609-612 2003 ICASSP (2) https://doi.org/10.1109/ICASSP.2003.1202440 conf/icassp/2003 db/conf/icassp/icassp2003.html#LiuM03 Ciaran McIvor Máire McLoone John V. McCanny A high-speed, low latency RSA decryption silicon core. 133-136 2003 conf/iscas/2003 ISCAS (4) https://doi.org/10.1109/ISCAS.2003.1205791 db/conf/iscas/iscas2003-4.html#McIvorMM03 Paul V. McCanny John V. McCanny Shahid Masud VLSI design and implementation of 2-D Inverse Discrete Wavelet Transform. 1-4 2002 EUSIPCO https://ieeexplore.ieee.org/document/7072288/ conf/eusipco/2002 db/conf/eusipco/eusipco2002.html#McCannyMM02 Máire McLoone John V. McCanny Efficient single-chip implementation of SHA-384 and SHA-512. 311-314 2002 FPT https://doi.org/10.1109/FPT.2002.1188699 conf/fpt/2002 db/conf/fpt/fpt2002.html#McLooneM02 Paul V. McCanny Shahid Masud John V. McCanny Design and implementation of the symmetrically extended 2-D Wavelet Transform. 3108-3111 2002 ICASSP https://doi.org/10.1109/ICASSP.2002.5745307 conf/icassp/2002 db/conf/icassp/icassp2002.html#McCannyMM02 Kok Sing Yap John V. McCanny A hybrid mixed cost-function TEQ initialization algorithm for ADSL modems. 4183 2002 ICASSP https://doi.org/10.1109/ICASSP.2002.5745652 conf/icassp/2002 db/conf/icassp/icassp2002.html#YapM02 Kok Sing Yap John V. McCanny A mixed cost-function adaptive algorithm for ADSL time-domain equalization. 1798-1802 2002 ICC https://doi.org/10.1109/ICC.2002.997158 conf/icc/2002 db/conf/icc/icc2002.html#YapM02

Shahid Masud John V. McCanny Design of Silicon IP Cores for Biorthogonal Wavelet Transforms. 179-196 2001 29 J. VLSI Signal Process. 3 https://doi.org/10.1023/A:1012279312716 db/journals/vlsisp/vlsisp29.html#MasudM01

Máire McLoone John V. McCanny High Performance Single-Chip FPGA Rijndael Algorithm Implementations. 65-76 2001 conf/ches/2001 CHES https://doi.org/10.1007/3-540-44709-1_7 db/conf/ches/ches2001.html#McLooneM01 Máire McLoone John V. McCanny Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm. 152-161 2001 conf/fpl/2001 FPL https://doi.org/10.1007/3-540-44687-7_16 db/conf/fpl/fpl2001.html#McLooneM01 Zhaohui Liu Gaye Lightbody Richard L. Walke Yi Hu John V. McCanny Generic scheduling methods for a linear QR array SoC processor. 1097-1100 2001 ICASSP https://doi.org/10.1109/ICASSP.2001.941111 https://doi.ieeecomputersociety.org/10.1109/ICASSP.2001.941111 conf/icassp/2001 db/conf/icassp/icassp2001.html#LiuLWHM01 Paul V. McCanny Shahid Masud John V. McCanny An efficient architecture for the 2-D biorthogonal discrete wavelet transform. 314-317 2001 conf/icip/2001 ICIP (3) https://doi.org/10.1109/ICIP.2001.958114 db/conf/icip/icip2001-3.html#McCannyMM01

Robert Hamill John V. McCanny Richard L. Walke Online CORDIC algorithm and VLSI architecture for implementing QR-array processors. 592-598 2000 48 IEEE Trans. Signal Process. 2 https://doi.org/10.1109/78.823992 db/journals/tsp/tsp48.html#HamillMW00

Gaye Lightbody Richard L. Walke Roger F. Woods John V. McCanny Linear QR Architecture for a Single Chip Adaptive Beamformer. 67-81 2000 24 J. VLSI Signal Process. 1 https://doi.org/10.1023/A:1008118711904 db/journals/vlsisp/vlsisp24.html#LightbodyWWM00

Shahid Masud John V. McCanny Wavelet packet transforms for system-on-chip applications. 3287-3290 2000 ICASSP https://doi.org/10.1109/ICASSP.2000.860102 https://doi.ieeecomputersociety.org/10.1109/ICASSP.2000.860102 conf/icassp/2000 db/conf/icassp/icassp2000.html#MasudM00

Tiong Jiu Ding John V. McCanny Yunsheng Hu Rapid design of application specific FFT cores. 1371-1381 1999 47 IEEE Trans. Signal Process. 5 https://doi.org/10.1109/78.757224 db/journals/tsp/tsp47.html#DingMH99

Gaye Lightbody Richard L. Walke Roger F. Woods John V. McCanny Novel mapping of a linear QR architecture. 1933-1936 1999 ICASSP https://doi.org/10.1109/ICASSP.1999.758303 https://doi.ieeecomputersociety.org/10.1109/ICASSP.1999.758303 conf/icassp/1999 db/conf/icassp/icassp1999.html#LightbodyWWM99 Shahid Masud John V. McCanny Rapid design of discrete orthonormal wavelet transforms using silicon IP components. 2167-2170 1999 ICASSP https://doi.org/10.1109/ICASSP.1999.758364 https://doi.ieeecomputersociety.org/10.1109/ICASSP.1999.758364 conf/icassp/1999 db/conf/icassp/icassp1999.html#MasudM99 Jill K. Hunter John V. McCanny Rapid design of discrete transform cores. 1-4 1998 EUSIPCO https://ieeexplore.ieee.org/document/7090000/ conf/eusipco/1998 db/conf/eusipco/eusipco1998.html#HunterM98 Shahid Masud John Vincent McCanny Finding a suitable wavelet for image compression applications. 2581-2584 1998 ICASSP https://doi.org/10.1109/ICASSP.1998.678050 conf/icassp/1998 db/conf/icassp/icassp1998.html#MasudM98 Jill K. Hunter John V. McCanny Discrete cosine transform generator for VLSI synthesis. 2997-3000 1998 ICASSP https://doi.org/10.1109/ICASSP.1998.678156 conf/icassp/1998 db/conf/icassp/icassp1998.html#HunterM98 Shahid Masud John V. McCanny Rapid Design of Discrete Orthonormal Wavelet Transforms. 142- 1998 conf/rsp/1998 International Workshop on Rapid System Prototyping https://doi.org/10.1109/IWRSP.1998.676683 https://doi.ieeecomputersociety.org/10.1109/IWRSP.1998.676683 db/conf/rsp/rsp1998.html#MasudM98

David W. Trainor Roger F. Woods John V. McCanny Architectural Synthesis of Digital Signal Processing Algorithms Using "IRIS". 41-55 1997 16 J. VLSI Signal Process. 1 https://doi.org/10.1023/A:1007908217284 db/journals/vlsisp/vlsisp16.html#TrainorWM97

John V. McCanny Douglas Ridge Yi Hu Jill K. Hunter Hierarchical VHDL libraries for DSP ASIC design. 675-678 1997 ICASSP https://doi.org/10.1109/ICASSP.1997.599858 https://doi.ieeecomputersociety.org/10.1109/ICASSP.1997.599858 conf/icassp/1997 db/conf/icassp/icassp1997.html#McCannyRHH97

Colin Chiu Wing Hui Tiong Jiu Ding John V. McCanny Roger F. Woods A 64-point Fourier transform chip for video motion compensation using phase correlation. 1751-1761 1996 31 IEEE J. Solid State Circuits 11 https://doi.org/10.1109/JSSC.1996.542320 db/journals/jssc/jssc31.html#HuiDMW96

Colin Chiu Wing Hui Tiong Jiu Ding John V. McCanny Roger F. Woods A New FFT Architecture and Chip Design for Motion Compensation based on Phase Correlation. 83-92 1996 conf/asap/1996 ASAP https://doi.org/10.1109/ASAP.1996.542804 https://doi.ieeecomputersociety.org/10.1109/ASAP.1996.542804 db/conf/asap/asap1996.html#HuiDMW96 B. D. E. Smith John V. McCanny Synthesisable high performance adaptive equaliser and Viterbi decoder for the Class-IV PRML channel. 25-28 1996 ICECS https://doi.org/10.1109/ICECS.1996.582638 conf/icecsys/1996 db/conf/icecsys/icecsys1996.html#SmithM96 Colin Chiu Wing Hui Tiong Jiu Ding John V. McCanny Roger F. Woods Error analysis of FFT architectures for digital video applications. 820-823 1996 ICECS https://doi.org/10.1109/ICECS.1996.584488 conf/icecsys/1996 db/conf/icecsys/icecsys1996.html#HuiDMW96

Stephen E. McQuillan John V. McCanny A Systematic Methodology for the Design of High Performance Recursive Digital Filters. 971-982 1995 44 IEEE Trans. Computers 8 db/journals/tc/tc44.html#McQuillanM95 https://doi.org/10.1109/12.403713 http://doi.ieeecomputersociety.org/10.1109/12.403713

M. Yan John V. McCanny Yi Hu VLSI architectures for vector quantization. 5-23 1995 10 J. VLSI Signal Process. 1 https://doi.org/10.1007/BF02407023 db/journals/vlsisp/vlsisp10.html#YanMH95

Stephen E. McQuillan John V. McCanny Fast VLSI algorithms for division and square root. 151-168 1994 8 J. VLSI Signal Process. 2 https://doi.org/10.1007/BF02109382 db/journals/vlsisp/vlsisp8.html#McQuillanM94

John V. McCanny Yi Hu M. Yan Automated design of DSP array processor chips. 33-44 1994 ASAP https://doi.org/10.1109/ASAP.1994.331818 conf/asap/1994 db/conf/asap/asap1994.html#McCannyHY94 Stephen E. McQuillan John V. McCanny Robert Hamill New algorithms and VLSI architectures for SRT division and square root. 80-86 1993 IEEE Symposium on Computer Arithmetic https://doi.org/10.1109/ARITH.1993.378106 conf/arith/1993 db/conf/arith/arith1993.html#McQuillanMH93

M. Yan John V. McCanny Systolic inner product arrays with automatic word rounding. 227-242 1992 4 J. VLSI Signal Process. 2-3 https://doi.org/10.1007/BF00925124 db/journals/vlsisp/vlsisp4.html#YanM92

Rajinder Jit Singh John V. McCanny High performance VLSI architecture for Wave Digital Filtering. 269-278 1992 4 J. VLSI Signal Process. 4 https://doi.org/10.1007/BF00930640 db/journals/vlsisp/vlsisp4.html#SinghM92

Stephen E. McQuillan John V. McCanny Algorithms and architectures for high performance recursive filtering. 230-244 1992 ASAP https://doi.org/10.1109/ASAP.1992.218569 conf/asap/1992 db/conf/asap/asap1992.html#McQuillanM92 B. P. McGovern Roger F. Woods John V. McCanny The systematic design of high performance digital filters. 609-612 1992 ICASSP https://doi.org/10.1109/ICASSP.1992.226546 conf/icassp/1992 db/conf/icassp/icassp1992.html#McGovernWM92 Rajinder Jit Singh John V. McCanny A wave digital filter three-port adaptor with fine grained pipelining. 116-128 1991 ASAP https://doi.org/10.1109/ASAP.1991.238889 conf/asap/1991 db/conf/asap/asap1991.html#SinghM91 O. C. McNally John V. McCanny Roger F. Woods A 40 megasample IIR filter chip. 416-430 1991 ASAP https://doi.org/10.1109/ASAP.1991.238905 conf/asap/1991 db/conf/asap/asap1991.html#McNallyMW91 John V. McCanny On the use of most significant digit first arithmetic in the design of high performance DSP chips. 243-260 1991 conf/ccc/1991 Algorithms and Parallel VLSI Architectures db/conf/ccc/ccc1991.html#McCanny91 O. C. McNally William P. Marnane John V. McCanny Design and test of a bit parallel 2nd order IIR filter structure. 1189-1192 1991 ICASSP https://doi.org/10.1109/ICASSP.1991.150593 conf/icassp/1991 db/conf/icassp/icassp1991.html#McNallyMM91 Stephen E. McQuillan John V. McCanny A VLSI architecture for multiplication, division and square root. 1205-1208 1991 ICASSP https://doi.org/10.1109/ICASSP.1991.150600 conf/icassp/1991 db/conf/icassp/icassp1991.html#McQuillanM91 O. C. McNally John V. McCanny Roger F. Woods Design of a Highly Pipelined 2nd Order IIR Filter Chip. 19-28 1991 conf/vlsi/1991 VLSI db/conf/vlsi/vlsi1991.html#McNallyMW91

John V. McCanny John G. McWhirter Sun-Yuan Kung The use of data dependence graphs in the design of bit-level systolic arrays. 787-793 1990 38 IEEE Trans. Acoust. Speech Signal Process. 5 https://doi.org/10.1109/29.56023 db/journals/tsp/tsp38.html#McCannyMK90

M. Yan John V. McCanny A bit-level systolic architecture for implementing a VQ tree search. 149-158 1990 2 J. VLSI Signal Process. 3 https://doi.org/10.1007/BF00935212 db/journals/vlsisp/vlsisp2.html#YanM90

Y. Hu John V. McCanny M. Yan Systolic VLSI compiler (SVC) for high performance vector quantisation chips. 145-155 1990 ASAP https://doi.org/10.1109/ASAP.1990.145451 conf/asap/1990 db/conf/asap/asap1990.html#HuMY90 Rajinder Jit Singh John V. McCanny Systolic two-port adaptor for high performance wave digital filtering. 379-388 1990 ASAP https://doi.org/10.1109/ASAP.1990.145474 conf/asap/1990 db/conf/asap/asap1990.html#SinghM90 M. Yan John V. McCanny Yi Hu VLSI architectures for digital image coding. 913-916 1990 ICASSP https://doi.org/10.1109/ICASSP.1990.115996 conf/icassp/1990 db/conf/icassp/icassp1990.html#YanMH90 Rajinder Jit Singh John V. McCanny Roger F. Woods Pipelined two-port adaptor for wave digital filtering. 1033-1036 1990 ICASSP https://doi.org/10.1109/ICASSP.1990.116078 conf/icassp/1990 db/conf/icassp/icassp1990.html#SinghMW90 O. C. McNally John V. McCanny Roger F. Woods Optimized bit level architectures for IIR filtering. 302-306 1990 ICCD https://doi.org/10.1109/ICCD.1990.130234 https://doi.ieeecomputersociety.org/10.1109/ICCD.1990.130234 conf/iccd/1990 db/conf/iccd/iccd1990.html#McNallyMW90

Simon C. Knowles John G. McWhirter Roger F. Woods John V. McCanny Bit-Level systolic architectures for high performance IIR filtering. 9-24 1989 1 J. VLSI Signal Process. 1 https://doi.org/10.1007/BF00932062 db/journals/vlsisp/vlsisp1.html#KnowlesMWM89

Simon C. Knowles John G. McWhirter Roger F. Woods John V. McCanny A bit-level systolic architecture for very high performance IIR filters. 2449-2452 1989 ICASSP https://doi.org/10.1109/ICASSP.1989.266963 conf/icassp/1989 db/conf/icassp/icassp1989.html#KnowlesMWM89 Roger F. Woods Simon C. Knowles John V. McCanny John G. McWhirter Systolic IIR filters with bit level pipelining. 2072-2075 1988 ICASSP https://doi.org/10.1109/ICASSP.1988.197037 conf/icassp/1988 db/conf/icassp/icassp1988.html#WoodsKMM88 S. M. F. Smyth John V. McCanny P. Challener An independent evaluation of the performance of the CCITT G.722 wideband coding recommendation using music signals. 2532-2535 1988 ICASSP https://doi.org/10.1109/ICASSP.1988.197159 conf/icassp/1988 db/conf/icassp/icassp1988.html#SmythMC88 S. M. F. Smyth John V. McCanny P. Challener An independent evaluation of the performance of the CCITT G.722 wideband coding recommendation. 2544-2547 1988 ICASSP https://doi.org/10.1109/ICASSP.1988.197162 conf/icassp/1988 db/conf/icassp/icassp1988.html#SmythMC88a

John V. McCanny John G. McWhirter Some Systolic Array Developments in the United Kingdom. 51-63 1987 20 Computer 7 https://doi.org/10.1109/MC.1987.1663620 http://doi.ieeecomputersociety.org/10.1109/MC.1987.1663620 db/journals/computer/computer20.html#McCannyM87

H. A. Kaouri John V. McCanny Transformed sub-band coding of speech using vector quantization. 2185-2188 1987 ECST https://doi.org/10.21437/ECST.1987-182 conf/interspeech/1987 db/conf/interspeech/ecst1987.html#KaouriM87 J. C. White John V. McCanny A. McCabe John G. McWhirter R. Evans A high speed CMOS/SOS implementation of a bit level systolic correlator. 1161-1164 1986 ICASSP https://doi.org/10.1109/ICASSP.1986.1168833 conf/icassp/1986 db/conf/icassp/icassp1986.html#WhiteMMME86 John V. McCanny Mapping system level functions on to bit level systolic arrays. 2159-2162 1986 ICASSP https://doi.org/10.1109/ICASSP.1986.1168628 conf/icassp/1986 db/conf/icassp/icassp1986.html#McCanny86 J. S. Ward John V. McCanny John G. McWhirter A systolic implementation of the Winograd Fourier transform algorithm. 1469-1472 1985 ICASSP https://doi.org/10.1109/ICASSP.1985.1168165 conf/icassp/1985 db/conf/icassp/icassp1985.html#WardMM85 David Beckett Holger Blume Keanhong Boey Dwayne Burns P. Challener Changlin Chen Yen-Kuang Chen Kevin Dickson Tiong Jiu Ding R. Evans Robert Hamill Y. Hu Yi Hu Yunsheng Hu Colin Chiu Wing Hui Jill K. Hunter H. A. Kaouri Simon C. Knowles Sun-Yuan Kung Friederich Kupzog Gaye Lightbody David W. Lin Yongping Liu Zhaohui Liu Liang Lu Ye Lu 0003 Yingxi Lu Lei Ma 0012 William P. Marnane Shahid Masud John McAllister A. McCabe Paul V. McCanny B. P. McGovern Ciaran McIvor Kieran McLaughlin O. C. McNally Stephen E. McQuillan John G. McWhirter Jun Mu Tobias G. Noll Máire O'NeillMáire McLoone Douglas Ridge Akashi Satoh Mathini Sellathurai Sakir Sezer Edwin H.-M. ShaEdwin Hsing-Mean Sha Rajinder Jit Singh B. D. E. Smith Neil Smyth S. M. F. Smyth Earl E. Swartzlander Jr. David W. Trainor Richard L. Walke J. S. Ward J. C. White Roger F. Woods M. Yan Xin Yang 0010 Kok Sing Yap Swee Yeow Yap