https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1653084/tms320f28388d-tms320f28388d-limitation-on-frequency-interrupt-triggered-by-ecap-or-hrcap-module/6384202Tue, 16 Jun 2026 10:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d851d92b-b9c7-4856-b0c9-9d1324ad78ffDivesh Dang 18431815Hi, I think that the next interrupt is getting generated while the ISR is being serviced. This might be a reason of GPIO not turning on consistently. Rather than using GPIO, you may try comparing the CAP register with the expected result. Thanks, Diveshhttps://e2e.ti.com/support/logic-group/logic/f/logic-forum/1655789/txs0108e-q1-inquiry-regarding-the-operational-characteristics-of-the-txs0108eTue, 16 Jun 2026 10:48:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:535838b0-ce3b-4ccd-82bd-7b9b3ea969c3DAEPYO HWANGPart Number: TXS0108E-Q1 Hello. "I am currently using a TXS series level shifter for I2C communication between an AP and an MCU. As shown in the waveform I’ve provided, there is a phenomenon where the signal stays at approximately 800mV for about 8ns during the falling edge. This behavior persists even after removing the external 2.2K pull-up resistors, but disappears when I pull the TXS OE pin to LOW. What could be the cause of this? Will this phenomenon affect I2C communication, and is it safe to continue using this product? I have one additional question regarding UART communication, for which I am also using a TXS series device. When I insert a 100-ohm damping resistor between the AP (UART TX) and the A-port, the same phenomenon—the signal holding at a specific voltage level—occurs. Replacing it with a 0-ohm resistor resolves the issue. Can I not use damping resistors with this device? I would appreciate your confirmation on these issues. Thank you."Infotainment & ClusterTXS0108E-Q1TXS0108Ehttps://e2e.ti.com/support/wireless-connectivity/wi-fi-group/wifi/f/wi-fi-forum/1655786/cc3351mod-2-4ghz-band-wi-fi-concurrent-usageTue, 16 Jun 2026 10:47:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:50fd3192-a865-4ec8-a52f-c0fa0f1d8817Fazle NabiPart Number: CC3351MOD Hi TI Team, We are planning to use the part number CC3351MODENIAMOZR . Could you confirm whether this part supports concurrent operation in the 2.4 GHz band for both Wi-Fi and BLE? Specifically, we want to verify that it can transmit and receive simultaneously at the 2.4 GHz frequency band for Wi-Fi and BLE. Thanks! Regards, Fazle NabiWireless InfrastructureCC3351MODhttps://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1652175/mspm0g5117-dfu-cannot-update-at-the-2ne-time/6384198Tue, 16 Jun 2026 10:46:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:582c15e5-2626-4225-bd23-662cb9395154Janz BaiBest Regards, Janz Baihttps://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1652175/mspm0g5117-dfu-cannot-update-at-the-2ne-time/6384196Tue, 16 Jun 2026 10:46:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:66ecc607-6702-4370-b850-093700840aa2Janz BaiHello Jerry, what is the difference between v2 and v3? In fact, as the README mentioned (in the SDK-> tools ->bsl -> dfu_host_utility), now we need to use the version 2.0 Zadig. I don't whether the v2 v3 customer mentioned means this version. But maybe need to confirm with customer. Best Regards, Janz Baihttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1655782/ucd8220-q1-request-for-shelf-life-details---ucd8220qpwprq1Tue, 16 Jun 2026 10:41:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:70b28ba6-0aea-485b-b61f-eb764eeec88aPraveen DPart Number: UCD8220-Q1 Hello TI Team, Good Day! I need Shelf-life details for the UCD8220QPWPRQ1. Please provide it ASAP. BR, D PraveenUCD8220-Q1https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1655781/bq40z50-r2-bq40z50-battery-meter-fcc-and-soh-low-issuesTue, 16 Jun 2026 10:38:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:95609df6-9231-4dbe-b47f-9a9f4ffabcdcRIJIA CHENPart Number: BQ40Z50-R2 Issue 1: Currently, we are encountering a problem of insufficient SOH (State of Health) and the updated Qmax reading is too low. However, the actual capacity of the battery itself is sufficient. Could you please advise on what factors could cause this issue? Also, could you provide suggestions on how to verify it? Regarding the issue of error accuracy of the Gauging IC, the following questions are raised. We kindly request your assistance in confirming and providing answers. Thank you! 1. What is the accuracy of the SOC (State of Charge) of the impedance tracking GAUGE? 2. What is the accuracy of the SOH (State of Health) of the impedance tracking GAUGE? 3. What is the accuracy of the QMAX (Maximum Q) of the impedance tracking GAUGE?bq40z50PC & NotebooksBQ40Z50-R2https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1655780/mspm0g3518-inquiry-regarding-lin-auto-baud-rate-configuration-parameters-mspm0g351x-mcalTue, 16 Jun 2026 10:36:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:857f18df-8314-448d-989b-f8c5f1aba669Mohamed AbdelfatahPart Number: MSPM0G3518 Hello TI Support Team, I am currently integrating the LIN MCAL driver for the MSPM0G3518 (using AUTOSAR version 4.4.0) and I have a few questions regarding the Auto Baud Rate configuration for a LIN Slave node. I see the LinChannelAutoBaudRate parameter which enables auto-baud detection for slave nodes. I would like more clarification on when to use this feature and how the underlying hardware utilizes the associated threshold and limit parameters: LinChannelAutoBaudRate (General Use Case): Could you clarify the exact practical scenarios where TI recommends enabling this feature versus using a fixed baud rate? Additionally, when enabled, does the hardware adapt the baud rate continuously on every received LIN sync byte, or only during initial communication/error recovery? LinChannelBaudRateLimit: If the incoming baud rate falls slightly outside this exact window, will the hardware reject the frame entirely, or does it trigger the LIN_E_TIMEOUT / hardware error? LinChannelAutoBaudRateTBitThreshold: This parameter configures the threshold number of 2Tbit cycle deviations (from 1 to 4). If we configure this to '2' (meaning auto baud rate happens if >= 2 cycles deviate from tolerance), how does the hardware handle the frame if the deviation is less than 2? Does it process the frame using the previously locked baud rate without adjusting? Hardware Clock Considerations: Are there any specific hardware clock configurations (e.g., specific LinChannelOversampling rates like 16X vs 8X) recommended to achieve the most reliable Auto Baud Rate detection on the MSPM0G351x? Thank you for your guidance! Best regards, Mohamed ABDELFATAH-MOHAMEDMSPM0G3518https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1655209/am62p-dual-display-same-content-with-different-resolution/6384192Tue, 16 Jun 2026 10:35:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e24274d9-6fbf-49e5-be1d-6384a5a36a04Kevin PengHi Shriya, As we discussed offline, customer is okay not using clone or mirror mode, just want to find a way achieving dual display same content with different resolution. We are thinking to read input frame buffer twice, 1 time to import to DPI DSS, 1 time to import to MIPI-DSI DSS, and inside the DSS we do the scale/resize and then output, could we have some guidance on this part please? Thanks, Kevinhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1655779/tpd1e10b06-pcn-number-20260611001-1---ti-part-no-tpd1e10b06dpyr-sanmina-part-no-fr1-w278-lfTue, 16 Jun 2026 10:35:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ca405985-189a-4b08-9497-db43bbd689edMarie CoghlanPart Number: TPD1E10B06 Hi In relation to PCN: 20260611001.1 for TI Part No. TPD1E10B06DPYR, Sanmina Part No. FR1-W278-LF We have a query from our Eng Dept with regards to this... The lead finish is changing from NiPDAu (Nickel-Palladium-Gold) to Sn (Tin) at the new manufacture site. The MSL is currently Level 1 but this change may move it to Level 3. NiPDAu (Nickel-Palladium-Gold) is used in medical, automotive, and aerospace applications, whereas SN is used in consumer, industrial, or commercial applications. FR1-W278-LF TPD1E10B06DPYR Does the MSL level change with the lead finish going from NiPDAu (Nickel-Palladium-Gold) to Sn (Tin) at the new site in TIEM ? Will the version of your # TPD1E10B06DPYR coming from the Tiem facility be denoted by a different MPN ? Will the version of your # TPD1E10B06DPYR still be available with the NiPDAu (Nickel-Palladium-Gold) lead finish from the current TI facility CDAT? Can you advise on above questions? Thanks MarieTPD1E10B06https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1655549/j721exsomxevm-j721exsomxevm-not-able-to-scan-micron-spi-flash-with-sf-probe/6384191Tue, 16 Jun 2026 10:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a28f2393-4d70-4aee-95b3-f6ffff0d4b94Diwakar DhyaniHi Abhrajit, Can you test with latest 11.2 SDK , i don't see this issue with that ? Regards Diwakarhttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1655711/tlv62090-incorrect-tina-simulation-for-tracking/6384190Tue, 16 Jun 2026 10:33:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e2500f7f-ad34-48bd-b174-f1cebc1da7fcAndrew CharnleyI know is has a tracking function on the SS pin. It works perfectly well as a current driver. Texas don't have a current driver that operates below 4.5v and at 2A hence my usage of the part.https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1655776/tps542021-24v-short-circuit-protection-by-tps542021Tue, 16 Jun 2026 10:30:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:265762cb-ed38-4cd3-8f16-94fe1b8d0d6cKavin ChungPart Number: TPS542021 Hello, I would like to design a 24V/1.2A output circuit with short circuit protection by TPS542021 in 24V system. I know there would be voltage drop by Rds (on) of N-MOS. I can accept that. Is there any risk to this design? Please let me know! Many thanks...building automationTPS542021https://e2e.ti.com/support/wireless-connectivity/bluetooth-group/bluetooth/f/bluetooth-forum/1651818/cc2340r5-critical-ota-flashing-issues-observed-with-simplelink-connect/6384188Tue, 16 Jun 2026 10:30:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3f0e271f-e874-4c3b-9094-419e35cf48efRatan DaleiHi Tarek, We have some additional observations regarding the OTA issue. While attempting to flash the firmware using OTA, we occasionally see the message "No OAD service found." In some cases, during the OTA update process, the application image appears to get erased, after which the device starts advertising as "Persistent App." When we subsequently attempt to perform the OTA update again, we receive the same "No OAD service found" message. Even after multiple retry attempts, the issue persists. This behavior is not observed consistently and appears to occur sporadically. Could you please clarify whether this behavior is expected? We understand that the Persistent App is intended to be a lightweight software image, however, we would like to understand why the OAD service is sometimes unavailable after the application image is erased and whether there is any recommended recovery mechanism for this scenario. Best regards, Ratan.https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1655397/am2634-am2634-evm-ccs-unable-to-halt-r5-core-error-2062-on-one-board-only-jtag-integrity-test-passes/6384186Tue, 16 Jun 2026 10:28:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d32a3f37-12ca-4e63-b964-958bd446c613nived karunHello TI team, Thank you for the detailed suggestions. We have tried the recommended steps and below are our observations: Force No‑Boot / DEVBOOT mode The board was configured to DEVBOOT / No‑Boot mode (SOP[3:0] = 1011) and power‑cycled. → The same Error ‑2062 (Unable to halt device) is observed even in No‑Boot mode. Power rail verification All the recommended test points show correct voltages: TP46 ≈ 5V TP38 ≈ 3.3V TP39 ≈ 1.2V The voltages are stable and comparable to the working AM2634 EVM. Attempt connection to other cores Debug connection was attempted to: R5FSS0‑1 Other available cores → The same Error ‑2062 is observed for all cores, indicating the issue is not limited to R5FSS0‑0. Erase boot flash using UniFlash Attempted to erase the QSPI flash using UniFlash via JTAG. → UniFlash fails to access memory and reports the same connection / emulation error , preventing flash erase. GEL / load_sbl.js execution With the board in DEVBOOT mode, attempted to run load_sbl.js from the MCU+ SDK using the CCS scripting console. The following error is consistently observed: Initializing .. (Completed) js:> loadJSFile("C:/ti/mcu_plus_sdk_am263x_09_01_00_41/tools/ccs_load/am263x/load_sbl.js") Error connecting to the target: emulation failure occurred (C:\ti\mcu_plus_sdk_am263x_09_01_00_41\tools\ccs_load\am263x\load_sbl.js#99) Repeating the command results in the same error.https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1655775/am2434-am243x-alternative-gpio-pin-selection-for-ethercat-phy-reset-tiesc_addonboardresetsequenceTue, 16 Jun 2026 10:26:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4685cf9d-8840-4a3c-814f-98caf17dd419sahar schwartzPart Number: AM2434 Hi, According to the EtherCAT SubDevice ICSSG0 Usage Guide document ( https://software-dl.ti.com/processor-industrial-sw/esd/ind_comms_sdk/am243x/2026_00_00_06/docs/am243x/ethercat_subdevice/_i_c_s_s_g0__usage__guide.html ), the GPIO_RESET_ICSS0_PHY1 and GPIO_RESET_ICSS0_PHY2 signals are expected to be assigned to pins GPMC0_CLK / R17 and GPMC0_ADVn_ALE / P16 . In our custom board design, these specific GPMC pins are already allocated for other functionalities. I would like to know, where should we we map these PHY reset signals? is it the ECAT_IN_nRST and ECAT_OUT_nRST? Thanks!AM2434Roboticshttps://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1654862/lp5860-question-about-key-scan-using-lp5860/6384182Tue, 16 Jun 2026 10:26:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9ab33655-4148-49eb-af07-a5faf763e19aKazuya Nakai59Hi Emma, Thank you very much for your reply. I attached a pdf file shows the connection between LP5860, LED and Switch. Can the both case connections control LED on/off and read each switch status without ghosting issue even 2 key rollover condition? Thank you again and best regards, Kazuya. e2e.ti.com/.../LP5860_5F00_LED_5F00_SW_5F00_position.pdfhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1649446/j722sxh01evm-ethernet-boot-failure-with-linux-sdk-11-02-00-06/6384181Tue, 16 Jun 2026 10:26:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:959e29df-7100-4d56-8fbe-7d7cc28a5a85Dharshan PHi Tanmay, Thanks for your response. I am using the J722SEVM board from TI. The DIP switch settings are configured as follows: SW2 [1-8] = 0000 0000 SW3 [1-8] = 1100 0100 SW4 [1-8] = 0000 1000 Please let me know if you need any additional information. Regards, Dharshanhttps://e2e.ti.com/support/processors-group/processors/f/processors-forum/1655772/am623-qspi-boot-fails-after-cold-resetTue, 16 Jun 2026 10:25:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:48c1b694-b5e5-4578-aa7c-1d047521ad5fKanaePart Number: AM623 Hi Support Team, The following issue has occurred on a custom board equipped with an AM6232 and a QSPI Flash device: MX25L25645GMI-08G (manufactured by Macronix). When BootMode=QSPI: QSPI boot proceeds normally after a warm reset, but fails after a cold reset (power restart). When BootMode=SPI, QSPI boot succeeds even after a Cold Reset (power restart). Upon observing the QSPI waveform with BootMode=QSPI using a logic analyzer, the following differences were confirmed. *During Warm Reset 1st Command: 0x9F (Read ID) Read Data: C2 20 19 C2 SPI Clock: 6MHz 2nd Command: 0x5A (SFDP Read) Address: 0x000000 Read Data: 53 46 44 50 (“SFDP”) SPI Clock: 6MHz The boot sequence proceeds normally thereafter. *During Cold Reset 1st Command: 0x9F (Read ID) Read Data: C2 20 19 C2 SPI Clock: 6MHz 2nd Command: 0x9F (Read ID) Read Data: C2 20 19 C2 SPI Clock: 52MHz After this, the boot process fails. While a Warm Reset proceeds to SFDP read (0x5A), a Cold Reset issues Read ID (0x9F) again, indicating a difference in behavior. Please let us know if there are any suspected causes or settings that should be checked regarding this issue. Best Regards, KanaeAM623https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1655635/lp-mspm0g3507-syscfg-error-popup-window-when-trying-to-assign-pin-to-adc12-and-opa-input/6384178Tue, 16 Jun 2026 10:24:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:33b7ded4-76d2-4a22-8392-a8e93f8dc1c7Zoey WeiHi Michael, Can you update the CCS version or sysconfig version... I checked from my side that I can succeeded in configuring them