Body effect

Structure of a planar n-channel MOSFET device (4 terminals).

The body effect (also known as substrate bias effect) is an undesired second-order effect present in field-effect transistors (MOSFET) that describes the change in transistor's threshold voltage ($V_{th}$) resulting from a potential difference between the source and the bulk (substrate) terminals. While ideal first-order MOSFET models assume that the source and bulk are tied to the same potential, in many integrated circuit topologies the source voltage varies dynamically while the substrate is kept at a global reference potential. This voltage difference alters the internal electrostatic balance of the device, strongly modifying the device biasing condition, switching characteristics and amplification capabilities.

Basic principle

The operation of any metal-oxide-semiconductor field-effect transistor relies on the precise modulation of energy bands at the semiconductor-oxide interface through an externally applied gate-to-bulk voltage ($V_{GB}$). This phenomenon is called field effect and enables the doping inversion of the semiconductor at the interface, thus allowing the creation of a conductive channel between the source and drain terminals. However, only a fraction of the externally applied voltage is actually employed to modulate the bands, while part of it drops across the oxide and presents a dependence on the amount of fixed charge exposed in the substrate due to the creation of the inversion layer.

When a non zero source-to-bulk voltage ($V_{SB}$) is applied, the electrical behavior of the channel area is altered. More precisely, a reverse bias between the source and the body widens the depletion layer beneath the gate oxide, increasing the density of uncompensated doping ions exposed by the field effect. This leads to a larger voltage drop across the entire oxide region. As a result, a higher $V_{GB}$, and therefore threshold voltage, is required to allow the formation of the inversion channel with respect to the $V_{SB}=0$ condition.

Physical framework

In an enhancement-mode nMOS device, with respect to the source-to-bulk voltage, it is possible to establish two possible conditions:

• neutral condition ($V_{SB}=0$)
• reverse body biasing ($V_{SB}>0$)

The forward body biasing condition ($V_{SB}<0$) is usually neglected as a valid operating regime as it generally fails to ensure off-state source-bulk and drain-bulk p-n junctions (diodes), therefore impairing the correct MOSFET operation. An equivalent argument can also be derived for the dual pMOS device.

Neutral condition (V_SB= 0)

Top panel: an externally applied $V_{GB}$ creates band bending (band diagram) depleting holes from the interface. A unique $E_{F}$ exists in the considered section. Bottom panel: The applied $V_{SB}$ splits the Fermi levels requiring a larger $V_{GB}$ to create an inversion channel.

Under zero body bias condition ($V_{SB}=0$) and when the drain and source terminals are cosidered at same electrostatic potential ($V_{DS}=0$), a single and constant Fermi level ($E_{F}$) exists across the entire substrate-channel structure. To establish a conduction channel between the source and drain, the energy bands must bend downward at the semiconductor-oxide interface. This strong inversion condition is reached when the surface potential satisfies the following equation:

$\phi _{s}=2|\phi _{F}|$

where ${\textstyle \phi _{s}}$ is called bulk Fermi potential, and defined as:

$\phi _{s}={\frac {k_{B}T}{q}}\ln {\bigg (}{\frac {N_{A}}{n_{i}}}{\bigg )}$

here, $k_{B}$ is the Boltzmann constant, $T$ is the absolute temperature expressed in Kelvin, $q$ is the elementary charge, $N_{A}$ is the substrate acceptor doping concentration in the bulk and $n_{i}$ is the intrinsic carrier concentration of the semiconductor.

The inversion charge induced at the interface, due to the externally applied voltage $V_{GB}$, can be expressed as:

$Q_{inv}=C_{ox}{\bigg (}V_{GB}-V_{FB}-\phi _{s}-{\frac {Q_{dep}(\phi _{s})}{C_{ox}}}{\bigg )}=C_{ox}(V_{GS}-V_{th0})$

where $C_{ox}$ is the gate oxide capacitance per unit area, ${\textstyle V_{FB}}$ is the flat band voltage of the device, ${\textstyle Q_{dep}}$ is the depletion charge density exposed in the substrate (depletion layer), while $V_{th0}$ is defined as the threshold voltage of the structure at zero substrate bias and it indicates the minimum ${\textstyle V_{GB}}$ needed to obtain an appreciable inversion charge (channel). Note that, since the source and bulk terminals are at the same electrostatic potential, the equation ${\textstyle V_{GB}=V_{GS}}$ holds.

Reverse body biasing (V_SB > 0)

When a positive source-to-bulk voltage is applied, the p-n junction formed by the p-type substrate and the n+ source region goes deeper into reverse-bias condition. This external bias drives the system out of thermodynamic equilibrium, causing the unique Fermi level to split into two distinct quasi-Fermi levels:

• $E_{Fp}$: the quasi-Fermi level for holes, anchored to the potential of the substrate.
• $E_{Fn}$: the quasi-Fermi level for electrons, which is pulled down by the higher potential of the source.

Since the source potential is higher with respect to the bulk, the energy level of the electrons in the source is lowered. This shifts $E_{Fn}$ in the source downwards with respect to $E_{Fp}$ in the bulk by an amount equals to $qV_{SB}$. In this circumstance, the bands must bend significantly more than they did at equilibrium to "chase" the shifted quasi-Fermi level of the source and in this way populate the conduction band. This translates into a higher threshold surface potential $\phi _{s}$ defined by the more general equality:

$\phi _{s}=2|\phi _{F}|+V_{SB}$

Given the higher surface potential needed, the amount of charge collected at the oxide-semiconductor interface becomes:

$Q_{inv}=C_{ox}{\bigg (}V_{GB}-V_{FB}-2|\phi _{F}|-V_{SB}-{\frac {Q_{dep}(2|\phi _{F}|+V_{SB})}{C_{ox}}}{\bigg )}$

that can be expressed in a more convenient way as a function of the threshold voltage $V_{th0}$ as:

$Q_{inv}=C_{ox}{\bigg (}V_{GS}-V_{th0}-{\frac {Q_{dep}(2|\phi _{F}|+V_{SB})-Q_{dep}(2|\phi _{F}|)}{C_{ox}}}{\bigg )}=C_{ox}(V_{GS}-V_{th})$

where $V_{th}$ is the general expression of the threshold voltage of the device in presence of body biasing.

As expected, the resulting threshold is modulated by the additional charge exposed in the substrate by the source-to-body voltage, while the last equation allows to derive a more comprehensive expression for $V_{th}$ as a function of $V_{SB}$, with no actual assumption regarding the doping profile employed in the bulk.

Threshold voltage

For a uniformly doped substrate, the dependence of the threshold voltage on the source-to-substrate voltage can be analytically modeled by the body effect equation

$V_{th}=V_{th0}+\gamma {\bigg (}{\sqrt {2|\phi _{F}|+V_{SB}}}-{\sqrt {2|\phi _{F}|}}{\bigg )}$

where $\gamma$ is the body effect coefficient expressed as:

$\gamma ={\frac {\sqrt {2\epsilon _{si}qN_{A}}}{C_{ox}}}$

here, $\epsilon _{si}$ is the permettivity of silicon.

This formulation is particularly insightful as it highlights how geometric and technological parameters dictate the influence of the body on the threshold voltage. Specifically, it demonstrates that the body effect scales with:

• doping concentration ($N_{A}$): a higher substrate doping increases the depletion charge, potentially intensifying the body effect;
• oxide thickness ($t_{ox}$): embedded within ${\textstyle C_{ox}={\frac {\epsilon _{ox}}{t_{ox}}}}$, a thinner oxide increases the gate control on the channel, thereby shielding it from unwanted body variations.

Small-signal model

Small-signal model MOSFET: the body transconductance $g_{mb}$ is modeled as a VCCS in parallel with main gate $g_{m}$ and from the point of view of a signal it behaves in the same way. Bulk terminal is not explicitly shown.

In analog circuits, variations in the bulk voltage modulate the threshold voltage of the device and consequentially modify its drain current ($I_{D}$) in a manner analogous to the gate terminal. This behavior can be modeled through a small-signal equivalent circuit by introducing a voltage-controlled current source driven by the body-source voltage.

Threshold voltage of an nMOS device as a function of the body-to-source voltage in typical MOS technology. As $V_{SB}$ increases the impact on $V_{th}$ is limited due to the nonlinear relation linking the two. $\eta$ is graphically represented as the tangent to the plot at $V_{SB}=0$.

More precisely, it is possible to define the body transconductance as:

$g_{mb}={\frac {\partial {I_{D}}}{\partial {V_{BS}}}}={\frac {\partial {V_{th}}}{\partial {V_{BS}}}}{\frac {\partial {I_{D}}}{\partial {V_{th}}}}=\eta g_{m}$

where $g_{m}$ is the small-signal gate transconductance of the MOSFET and $\eta$ ( typically ranging from 0.1 to 0.3) represents the ratio between the body transconductance and its gate equivalent. Its expression can be directly derived from the body effect equation, yielding:

$\eta ={\frac {\partial {V_{th}}}{\partial {V_{BS}}}}={\frac {\gamma }{2{\sqrt {|2\phi _{F}|+V_{SB}}}}}={\frac {C_{dep}}{C_{ox}}}{\bigg |}_{V_{SB}=0}$

It is worth noting that $\eta$ not only provides a way to quantify the body contribution to the drain current but it is also a compact measure of the threshold voltage sensitivity to any $V_{SB}$ variation.

Although typically negligible compared to the gate transconductance, the body transconductance provides a decoupled path to modulate the drain current, allowing the substrate to be leveraged as an alternative input for signal operation and control.

Impact on IC design

Historically, the body effect is categorized as a non-ideal parasitic effect, introducing severe design constraints in both digital and analog design. More precisely, the most common drawbacks resulting from body biasing are:

• Performance reduction in analog circuits: in degenerated common-source configurations or in source follower subcircuits, the substrate effect contributes to lowering the overall voltage gain of the configurations and worsening the linearity due to the non-linear dependance of $V_{th}$.

• Performance degradation in digital circuits: in logic gates (such as NAND/NOR gates or pass-transistor logic), pull-up or pull-down networks utilize series-connected transistors. In these structures, some of the devices do not experience zero source-to-bulk voltage ($V_{SB}=0$). The resulting threshold voltage modulation due to body effect decreases the available overdrive voltage of the device, degrading propagation delays and reducing the switching speed of the logic gates.

Advanced applications and modern architectures

In modern microelectronics, the capability to intentionally modulate the threshold voltage through the substrate terminal has transformed the body effect from an unwanted parasitic phenomenon into an alternative design tool that can be intentionally exploited to improve chip design.

Back gate control in FD-SOI technologies

Structure of a FD-SOI nMOS device. The additional $SiO_{2}$ layer provides the isolation BOX enabling independent body biasing.

In fully-depleted silicon on insulator technologies (FD-SOI), the transistor channel is fabricated on a very thin layer of fully depleted silicon, which is electrically isolated from the substrate by a BOX layer (buried oxide). In this case, the substrate acts as an isolated second gate for the MOSFET and it is often referred to as back-gate.

Applying a potential to the back-gate vertically shifts the energy bands within the channel, modifying $V_{th}$ with significantly greater efficacy than in bulk planar devices. In particular, this architecture enables dynamic body biasing (DBB), greatly boosting the efficiency of FD-SOI digital blocks through:

• forward body biasing (FBB): applying a forward bias to the back-gate ($V_{SB}<0$) decreases the magnitude of the substrate effect. As a consequence the overdrive of the MOS structures increases, allowing a more conductive behavior of the devices and better switching performances of the logic gates. It is important to note that this approach is possible only when carefully taking into account the limits coming from the turn-on of the parasitic source-bulk and drain-bulk diodes of the device.
• reverse body biasing (RBB): applying a reverse bias ($V_{SB}>0$) causes an increase in the threshold voltage $V_{th}$, mitigating the leakage subthreshold currents of the off-devices and allowing the logic blocks to enter an extremely low power standby state.

Ultra-low power (ULP) and ultra-low voltage (ULV) circuits

Scheme of a simple fully differential bulk-driven OTA.

For applications targeting the IoT (Internet of things), implantable biomedical sensors, or energy-harvesting systems, supply voltages are reduced to near or below the nominal threshold voltage ($V_{DD}$ values ranging between $0.3V$ and $0.5V$). In this extreme regime, the supply voltage does not allow for conventional gate-driven topologies as they fail to guarantee an acceptable input dynamic. To circumvent this limitation, the input signal can be applied directly to the body terminal, while the gate is held at a constant DC bias maintaining the device in weak inversion condition. This approach, usually referred to as bulk-driven MOSFET design, completely relies on the body transconductance, and thus requires a dedicated well for the bulk to guarantee its isolation from the substrate of the chip. Although these topologies introduce major trade-offs, mainly due to the weaker transconductance factor with respect to the main gate action, they potentially enable wide (almost rail-to-rail) input swings while still preserving a linear operation.
Some of these drawbacks can be mitigated by boosting the overall voltage gain of the stages through cascoded topologies or by applying local positive feedback techniques embedded within the input stage.

See also

• Channel length modulation
• Drain-induced barrier lowering
• EKV MOSFET model
• Fin field-effect transistor
• Floating body effect
• MOSFET operation
• Threshold voltage

External links

• MOSFET threshold voltage notes
• MOSFET body effect notes
• Analog design lectures by Behzad Razavi
• Introduction to nanoelectronics MIT edu - electron devices