This is a real time clock, an integrated circuit, provides time to the microcontroller.It consists of oscillatory circuit, counter, register. Oscillatory circuit made of quartz crystal generates clock signal with high level of stability. Prescaler also called as frequency divider scales the clock producing a clock of frequency 1Hz. Counter using generated 1Hz clock signal counts the seconds and apparently minutes, hours. The time values are stored in a register. Real-time circuit is interfaced with microcontroller by Advanced Peripheral Bus following Advanced Microcontroller Bus Architecture (AMBA) bus protocol there by communicating time with microcontroller. Real-time clock provides accurate time track to the device so all the events take place at the right time. This system functions reliably with optimum CPU and memory space usage.
Open terminal and type the following commands to install iverilog and GTKwave.
$ sudo add-apt-repository ppa:team-electronics/ppa
$ sudo apt-get update
$ sudo apt-get install iverilog gtkwave
$ git clone https://github.com/Bandaanusha/iiitb_rtc
$ cd iiitb_rtc
$ iverilog -o iiitb_rtc_out.out iiitb_rtc.v iiitb_rtc_tb.v
$ vvp iiitb_rtc_out.out
$ iverilog iiitb_rtc.v iiitb_rtc_tb.v
$ gtkwave iiitb_rtc_out.vcd
Synthesis transforms the simple RTL design into a gate-level netlist with all the constraints as specified by the designer. In simple language, Synthesis is a process that converts the abstract form of design to a properly implemented chip in terms of logic gates. Yosys is a framework for Verilog RTL synthesis.
Open the terminal and type the following commands to install yosys
$ sudo apt-get install build-essential clang bison flex \ libreadline-dev gawk tcl-dev libffi-dev git \ graphviz xdot pkg-config python3 libboost-system-dev \ libboost-python-dev libboost-filesystem-dev zlib1g-dev
$ make
$ sudo make install
> read_liberty -lib /home/anusha/iiitb_rtc/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
> read_verilog iiitb_rtc.v
> synth -top iiitb_rtc
> dfflibmap -liberty /home/anusha/iiitb_rtc/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
> abc -liberty /home/anusha/iiitb_rtc/lib/sky130_fd_sc_hd__tt_025C_1v80.lib -script +strash;scorr;ifraig;retime,{D};strash;dch,-f;map,-M,1,{
> write_verilog iiitb_rtc_netlist.v
GLS is generating the simulation output by running test bench with netlist file generated from synthesis as design under test. Netlist is logically same as RTL code, therefore, same test bench can be used for it.
$ iverilog /home/anusha/iiitb_rtc/verilog_model/primitives.v /home/anusha/iiitb_rtc/verilog_model/sky130_fd_sc_hd.v iiitb_rtc_netlist.v iiitb_rtc_tb.v
$ ./a.out
$ gtkwave iiitb_rtc_out.vcd
Pre - synthesis simulation waveform:
Post - synthesis simulation waveform:
$ sudo apt install -y build-essential python3 python3-venv python3-pip
$ sudo apt-get remove docker docker-engine docker.io containerd runc (removes older version of docker if installed)
$ sudo apt-get update
$ sudo apt-get install \
ca-certificates \
curl \
gnupg \
lsb-release
$ sudo mkdir -p /etc/apt/keyrings
$ curl -fsSL https://download.docker.com/linux/ubuntu/gpg | sudo gpg --dearmor -o /etc/apt/keyrings/docker.gpg
$ echo \
"deb [arch=$(dpkg --print-architecture) signed-by=/etc/apt/keyrings/docker.gpg] https://download.docker.com/linux/ubuntu \
$(lsb_release -cs) stable" | sudo tee /etc/apt/sources.list.d/docker.list > /dev/null
$ sudo apt-get update
$ sudo apt-get install docker-ce docker-ce-cli containerd.io docker-compose-plugin
$ apt-cache madison docker-ce (copy the version string you want to install)
$ sudo apt-get install docker-ce=<VERSION_STRING> docker-ce-cli=<VERSION_STRING> containerd.io docker-compose-plugin (paste the version string copies in place of <VERSION_STRING>)
$ sudo docker run hello-world (If the docker is successfully installed u will get a success message here)
$ git clone https://github.com/The-OpenROAD-Project/OpenLane.git
$ cd OpenLane/
$ make
$ make test
Additional packages to be installed as a part of system requirements to compile magic before magic installation.
$ sudo apt-get install m4
$ sudo apt-get install tcsh
$ sudo apt-get install csh
$ sudo apt-get install libx11-dev
$ sudo apt-get install tcl-dev tk-dev
$ sudo apt-get install libcairo2-dev
$ sudo apt-get install mesa-common-dev libglu1-mesa-dev
$ sudo apt-get install libncurses-dev
$ git clone https://github.com/RTimothyEdwards/magic
$ cd magic
$ ./configure
$ make
$ make install
$ sudo apt-get install klayout
Creating iiitb_rtc design file in openlane directory
$ cd OpenLane
$ cd designs
$ mkdir iiitb_rtc
$ mkdir src
$ cd src
$ touch iiitb_rtc.v
$ cd ../
$ touch config.json
Config.json File
{
"DESIGN_NAME": "iiitb_rtc",
"VERILOG_FILES": "dir::src/iiitb_rtc.v",
"CLOCK_PORT": "clkin",
"CLOCK_NET": "clkin",
"GLB_RESIZER_TIMING_OPTIMIZATIONS": true,
"CLOCK_PERIOD": 10,
"PL_TARGET_DENSITY": 0.7,
"FP_SIZING" : "relative",
"LIB_SYNTH": "dir::src/sky130_fd_sc_hd__typical.lib",
"LIB_FASTEST": "dir::src/sky130_fd_sc_hd__fast.lib",
"LIB_SLOWEST": "dir::src/sky130_fd_sc_hd__slow.lib",
"LIB_TYPICAL": "dir::src/sky130_fd_sc_hd__typical.lib",
"TEST_EXTERNAL_GLOB": "dir::../iiitb_rtc/src/*",
"SYNTH_DRIVING_CELL":"sky130_vsdinv",
"pdk::sky130*": {
"FP_CORE_UTIL": 30,
"scl::sky130_fd_sc_hd": {
"FP_CORE_UTIL": 20
}
}
}
Including sky130_vsdinv cell to the design
$ cd OpenLane
$ cd vsdstdcelldesign
$ cp sky130_vsdinv.lef /home/anusha/OpenLane/designs/iiitb_rtc/src
$ cd libs
$ cp sky130_fd_sc_hd__* /home/anusha/OpenLane/designs/iiitb_rtc/src
Invoking openlane tcl console
$ cd OpenLane
$ ./flow.tcl -interactive
In tcl console commnd to load openlane package
% package require openlane 0.9
Preparing design
% prep -design iiitb_rtc
The following commands are to merge external the lef files to the merged.nom.lef. In our case sky130_vsdinv is getting merged to the lef file
% set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
% add_lefs -src $lefs
Type the command on tickle after preparing design to synthesize design
% run_synthesis
Statistics
Slack
Command to run the floorplan
% run_floorplan
Command to view floorplan on magic
magic -T /home/anusha/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.nom.lef def read iiitb_rtc.def
Floorplan
Core area
Die area
Command to run placement
% run_placement
Command to view placement on magic
magic -T /home/anusha/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.nom.lef def read iiitb_rtc.def
Placement
Placement of sky130_vsdinv cell
Command to run clock-tree synthesis
run_cts
Command to run routing
run_routing
Routing of sky130_vsdinv cell
Gate Count = 133
Flop Ratio = Ratio of total number of flip flops / Total number of cells present in the design = 24/133 = 0.1804
Area = 9941.292 um2
Internal Power = 169 uW (73.8%)
Switching Power = 601 uW (26.2%)
Leakage Power = 0.934 nW (0.0%)
Total Power = 229 uW (100%)
Performance = 1/(clock period - slack) = 1/(10 - 2.71)ns = 137.17 Mhz
- Banda Anusha
- Kunal Ghosh
- Madhav Rao, Professor
- Nanditha Rao, Professor
- Kunal Ghosh, Director, VSD Corp. Pvt. Ltd.
- Madhav Rao, Professor, IIITB
- Nanditha Rao, Professor, IIITB
- Banda Anusha, Postgraduate Student, International Institute of Information Technology, Bangalore Banda.Anusha@iiitb.ac.in
- Dantu Nandini Devi, Postgraduate Student, International Institute of Information Technology, Bangalore nandini.dantu@gmail.com
- Kunal Ghosh, Director, VSD Corp. Pvt. Ltd. kunalghosh@gmail.com
- Nanditha Rao, nanditha.rao@iiitb.ac.in
- Madhav Rao, mr@iiitb.ac.in
- Real-Time Clocks (RTCC) ,Microchip technology, https://www.microchip.com/en-us/products/clock-and-timing/components/real-time-clocks.
- RTC Verilog Code - Elecdude, www.elecdude.com.
