This project focusses on designing a low power and efficient DAC design in Cadence. For DAC topology C2C architecture of 10bit resolution is chosen over binary-weighted architecture because of its remarkable speed and higher bandwidth, at a cost of distortions caused by parasitic capacitances.

• 1. Introduction to C2C DAC
• 2. C2C DAC architecture with DAC switches
• 3. Schematic of DAC_switch
• 4. IP Design Specifications
• 5. Simulation Results
  • DAC Switch
  • 1-Bit DAC subcircuit
  • 2-Bit DAC subcircuit
  • 3-Bit DAC subcircuit
  • 4-Bit DAC subcircuit
  • 5-Bit DAC subcircuit
  • 6-Bit DAC subcircuit
  • 7-Bit DAC subcircuit
  • 8-Bit DAC subcircuit
  • 9-Bit DAC subcircuit
  • 10-Bit-DAC
• 6. Schematic for Layout
• 7. Layout

DACs convert discrete digital signals into continuous analog signals. Among all the DAC architectures Capacitive DACs are preferred because of their reduced design complexity, optimized power and improved matching. Exclusively for medium to high resolution applications capacitive DACs are chosen over resistive and current steering DACs. Even though the Capacitive DAC based solution provides many benefits, it still faces a bottleneck in sizing the capacitors, capacitor mismatch and parasitic capacitance degrading the DAC performance. With technology scaling, digital solutions will also provide better portability between IC fabrication technologies and flexibility, and ultimately result in lower power and cost.

DAC switches take the digital bits as inputs and switch the output voltage in between Vref and GND. If the digital bit is ‘1’ then M1 and M2 transistors will be ON, transistors M3 and M4 will be OFF. This makes the switch output raise to Vdd. If the digital bit is ‘0’ then M3 and M4 transistors will be ON, transistors M1 and M2 will be OFF. This makes the switch output fall to ground voltage.

Switches are used to switch the output voltage in between Vdd and GND based on the digital bits.

As seen in Schematic, digital inputs are the control terminals to the switches of a DAC. Switches are used to switch the output voltage in between Vdd and GND based on the digital bits.

The logic of this switch is implemented using a 2 to 1 MUX.

DAC switches take the digital bits as inputs and switch the output voltage in between Vref and GND.

Based on the digital bits output of DAC is calculated as: 𝑉𝑜𝑢𝑡𝐶𝑡𝑜𝑡𝑎l = 𝐶𝑒𝑓𝑓𝑒𝑐𝑡𝑖𝑣𝑒 ∗ 𝑉𝑟𝑒𝑓 ∗ (∑𝑏𝑖2^(−(𝑁−𝑖))) , where bi is the digital input bits from Pulse input. Ctotal is the effective output capacitance of the entire C2C ladder network which is equal to 2Cu where Cu is the unit capacitance.

The output here reaches to 900mV based on the calculations.

Total capacitance spread of the C2C 10-bit DAC is 29Cu which is drastically low compared to binary weighted capacitor array DAC which will have a total of 1024Cu capacitance.

Here v0 is the LSB bit and v9 acts as MSB. The inputs are provided using a pulse Signal. The Output waveform showing the Output reaching 1.8V with smaller steps.

For DAC topology C2C architecture of 10bit resolution is chosen over binary-weighted architecture because of its remarkable speed and higher bandwidth, at a cost of distortions caused by parasitic capacitances.

Waveforms showing Actual and Ideal Outputs:

DNL and INL Characteristics:

Characteristics Table:

The schematic obtained by replacing all the voltage sources is as:

The obtained layout is as:

• Kavya Agarwal
• Kunal Ghosh

• Kunal Ghosh, Director, VSD Corp. Pvt. Ltd.
• Steven Bos

• Kavya Agarwal, Postgraduate Student, International Institute of Information Technology, Bangalore kavya11.ag@gmail.com
• Kunal Ghosh, Director, VSD Corp. Pvt. Ltd. kunalghosh@gmail.com

• The post layout simulation has to be carried out for the design.

• kunalg123/avsddac_workshop
• Wright State University - 10 bit DAC Design