The project aims to design a 10-bit Potentiometric Digital to Analog Converter using Cadence tools with scl 180nm technology node.

Here are the specifications from SPECS DOCUMENT

Digital-to-Analog-Converter (DAC) systems are ubiquitous. They are needed to interface digital or discrete signals -- typically binary such as VDD and GND, to the physical, analog world that uses a continuous range of signals. DACs and their counterpart Analog-to-Digital-Converter (ADC)s are thus found in most electrical systems. Practical applications are found in process control, programmable voltage sources, communication systems, data acquistions systems and many more. Commercial DACs range from 4-bit DAC to ultra high precision 24-bit DAC (and higher) to fast 22M Samples/Sec and 16-bit precise DAC. In this repository I present the building blocks of a 10-bit DAC with requirements that are typical for integration in modern Systems-on-a-Chip (SoC). Various analog designs can found such as an inverter, up/down shifters, analog switch and various n-bit DAC's. They are presented including their Virtuoso simulation behavior using 130nm scl 180nm technology node.

This project is part of the Mixed Signal design of ASIC's Course in IIIT Bengaluru Masters program taught by VLSI System Design Founder, Professor Kunal Gosh.

• 1. Introduction to Potentiometric Digital to Analog Converter
• 2. Operating principle
• 3. Characteristics
• 4. Potentiometric DAC Architecture Design
• 5. IP Design Specs
• 6. Pre-layout and Simulations
  • A. 1-Bit DAC subcircuit
  • B. 2-Bit DAC subcircuit
  • C. 3-Bit DAC subcircuit
  • D. 4-Bit DAC subcircuit
  • E. 5-Bit DAC subcircuit
  • F. 6-Bit DAC subcircuit
  • G. 7-Bit DAC subcircuit
  • H. 8-Bit DAC subcircuit
  • I. 9-Bit DAC subcircuit
  • J. 10-Bit-DAC
  • Prelayout Characterization
• 7. Layout and Future work
• 8. Contributors
• 9. Acknowledgments
• 10. Contact Information
• 11. References

The operating principle of a DAC shown in Fig. 1 is to convert a digital input code to an analog output signal. The input code open or close switches such that the correct output signal is created from a positive voltage reference or source typically called VREF. The negative reference can be ground or a negative voltage reference.

The smallest signal increments, the stepsize also called delta's or 1 Least Significant Bit (LSB) can be uniform (linear DAC) or logarithmic (log DAC) but should always be monotonic.

To analyze and compare DACs often four DC errors (static error characteristics) (Chapter 2, page 2.15 from the Data Conversion Handbook) are computed using the sampled and ideal transfer function:

• Offset and Gain error.

Image credits: Data Conversion Handbook

The offset or shift error can be seen when the transition from DAC output value to the next one is consistently off by a certain value. To calculate the offset error we take the sampled DAC output at t=0 and take the difference to the ideal DAC output at t=0. The gain or slope error can be seen when the DAC output has its offset error removed and is compared to the ideal slope. To calculate the gain error: sampled DAC output at t=n - sampled DAC output at t=0 - (2^{^n} - 1 LSB).

• Differential non-linearity (DNL).

Image credits: Original source All About Circuits, adapted from the Data Conversion handbook

How much is the difference between the sampled step height at t=x+1 and the previous sampled step height at t=x compared to the ideal step height of 1 LSB? The difference or deviation per input code is measured in LSB units. 1 LSB = FS/2^{^n}. For example, the DAC output at input code 010 has a height of 3.5 LSB while the DAC output at 001 is 1 LSB. The difference is 2.5 LSB. Compared to the ideal step size this is an increase (error) of +1.5 LSB. The DNL can be plotted over the entire input code range. If the DNL has only positive terms over the entire input range, the DAC is considered to be monotonic over the full scale (FS) output range, a desired property.

• Integral non-linearity (INL).

Image credits: Data Conversion Handbook

How much is the difference between the sampled step height at t=x and the ideal step height at t=x? The difference or deviation per input code is measured in LSB units. For example, in the DNL image at code 011 we eyeball that the sample is 4.5 LSB, while the previous sample was 3.5 LSB which is a perfect 1 LSB increase and thus a DNL error of 0. However, when we compute the INL we see that the ideal sample height is not 4.5 LSB but 3 LSB, meaning a INL error of + 1.5 LSB. The INL can be plotted over the entire input code range. For both the INL and the DNL the compensated sample output should be used which can be calculated as sample output - offset error - (n/(2^{^n}-1 LSB)) * gain error (see example from UiO IN5220 course material)

In SPICE simulation the transfer function can be aqcuired using a transient analysis, plotting time on the x-axis and DAC output on the y-axis. The DAC input or binary code start at all zero and and is incremented by 1 bit at fixed periods using a PWL or Pulse signal generator. The simulation time should be long enough to reach a steady state (DC) such that we can sample it. With Xschem, the INL and DNL metrics can be directly calculated and visualised from the raw simulated data, saving an export step to data processors and graphing tools such as Excel or Matlab.

The basic idea is to divide the voltage into N different voltage values in the range of Vref+ and Vref- for an N-Bit DAC. The design used here to achieve this is the simple resistor string DAC which consists of resistors in series. These resistors are then connected to various switches in such a fashion that it routes the exact voltage to the output.

The problem of the largeness of the circuit is reduced by building hierarchical subcircuits of switch, 2 Bit, 3 Bit, 4 Bit,....., 9 Bit DAC, and then two 9 Bit DAC is used to build the 10-Bit potentiometric DAC.

Have a look at the simplified architecture for potentiometric-DAC given below

Given below is the block diagram of the DAC -

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Source: Analog Devices

INL-LSB vs Digital Code Graph for 10-Bit DAC

• From Above plot Offset Error is Zero and Gain Error is -0.006457

DNL-LSB vs Digital Code Graph for 10-Bit DAC

Layout design plays a fundamental role in the development of Potentiomentric Digital to Analog Converter. , enabling the translation of a circuit schematic into a geometric representation that can be fabricated. In this particular case, the layout has been meticulously crafted using Cadence Virtuoso Layout XL, an advanced and feature-rich software tool designed specifically for IC layout design.

Cadence Virtuoso Layout XL offers a wide range of capabilities and features, empowering designers to create intricate and optimized layouts for complex integrated circuits. The software provides an intuitive and user-friendly environment, allowing designers to efficiently manipulate and arrange the various components of the circuit, including transistors, interconnects, and other circuit elements. With the assistance of Cadence Virtuoso Layout XL, designers can precisely position and connect the circuit elements, ensuring that the layout adheres to the design specifications, electrical constraints, and manufacturing rules.

Figure: Layout of 1Bit PotDAC or 1-channel analog switch or 2:1 analog MUX

The above figure provides a visual representation and detailed explanation of the layout design for a single-channel analog switch. This layout diagram serves as a valuable tool for understanding the physical arrangement and connectivity of the various components within the analog switch.

The layout of the analog switch involves the integration of 16 transistors, each having different widths to fulfill specific functional requirements. These transistors, collectively, form the building blocks of the analog switch circuitry and contribute to its overall performance.

The layout figure, prominently displayed in the bottom left corner, presents a clear depiction of the physical organization of the transistors within the analog switch.

Figure: Layout of 2-Bit-PotDAC

The above figure showcases the layout design of a 2-bit Potentiometric DAC, which serves the purpose of converting digital signals into corresponding analog voltage levels. This layout diagram provides a comprehensive visual representation of the physical arrangement and connectivity of the various components within the Potentiometric DAC circuit.

The layout incorporates three single-channel analog switches, which play a crucial role in selectively connecting the input voltage sources and the resistive ladder network to generate the desired analog output voltage. The switches facilitate the controlled routing of signals and enable the establishment of precise voltage levels based on the digital input.

Additionally, the layout incorporates four resistors, which are fundamental elements of the resistive ladder network. The resistors are carefully placed and connected in a specific configuration to ensure the accurate division of the reference voltage across multiple levels, thereby generating the desired analog output.

The figure prominently displays the interconnections between the 48 transistors, which are essential for the proper functioning of the Potentiometric DAC. These transistors collectively contribute to the implementation of the switching mechanism and signal routing required for generating the analog output.

Furthermore, the layout diagram features four input ports, namely D0, D1, VrefHigh, and VrefLow, which allow external signals to be inputted into the Potentiometric DAC and one output port, which represents the analog output voltage generated by the Potentiometric DAC.

Figure: Final Layout of PotDAC

In a similar manner to the 2-bit Potentiometric DAC discussed earlier, the concept of Potentiometric DACs can be extended to accommodate higher-resolution conversions. By leveraging the same principles and design techniques, it is possible to construct Potentiometric DACs with varying bit resolutions, such as 3, 4, 5, 6, 7, 8, and 9 bits. The above figure is the final layout representation of a 10-bit Potentiometric DAC and following figures are it's magnified versions.

Figure: Lavel~1 Magnifiged picture of Final Layout

Figure: Lavel~2 Magnifiged picture of Final Layout

Figure: Lavel~3 Magnifiged picture of Final Layout

Figure: Lavel~4 Magnifiged picture of Final Layout

Figure: Lavel~5 Magnifiged picture of Final Layout

Figure: Lavel~6 Magnifiged picture of Final Layout

The preliminary characterization and simulations of the design have been conducted successfully, yielding positive results. This signifies that the design has undergone initial testing and evaluation, providing valuable insights into its performance and functionality. With the completion of these preliminary steps, the design is now ready to proceed to the next stage, which involves transferring it to the proper layout.

During the layout stage, the design is translated into a physical representation, with components being placed and interconnected to create an optimized layout that meets the design specifications. However, in the present case, certain steps like Design Rule Check (DRC), Layout Versus Schematic (LVS), and post-layout simulations in the layout process are still pending due to integration issues with the SCL180nm Process Design Kit (PDK).

• Sanampudi Gopala Krishna Reddy
• Kunal Ghosh

• Kunal Ghosh, Director, VSD Corp. Pvt. Ltd.
• Steven Bos

• Sanampudi Gopala Krishna Reddy, Postgraduate Student, International Institute of Information Technology, Bangalore svgkr7@gmail.com
• Kunal Ghosh, Director, VSD Corp. Pvt. Ltd. kunalghosh@gmail.com

• kunalg123/avsddac_workshop