This project simulates the bidirectional up/down counter.We can generate an up or down counter using an external input

A bidirectional counter is a sequential up/down That has the ability to count in both directions Either from some preset value as well as zero. In This up/down counter an external input is used for Using either up or down mode. Counter that can count in both directions either Up or Down depending on the state of their input control pin and these are known as Bidirectional Counters.

1.This type of counter can be utilized as a self-reversing counter.
2.This counter can also be used as a clock divider circuit.
3.This type of counter is used in car parking slots.
4.These counters are used for low noise emission and low power applications.
5.These are used as frequency dividers.

In this circuit we are making a two bit up down counter using jk flip flops and an external input X is used to use either up or down counter.
When we use X = 0 our counter behaves as an up counter ,it advances in the sequence (0 , 1 ,2 ,3) and then back again to zero and when X= 1 counter moves in reverse sequence(3,2,1,0) .Generally, most bidirectional counters can be made to change their count Direction up or down at any point of time.This counter can be synchronously incremented or decremented based on the CLK transition from low to high

Icarus Verilog is an implementation of the Verilog hardware description language

GTKWave is a fully featured GTK+ v1. 2 based wave viewer for Unix and Win32 which reads Ver Structural Verilog Compiler generated AET files as well as standard Verilog VCD/EVCD files and allows their viewing

Open your terminal and type the following to install iverilog and GTKWave

$   sudo apt-get update
$   sudo apt-get install iverilog gtkwave

To clone the Repository and download the Netlist files for Simulation, enter the following commands in your terminal.

$ git clone https://github.com/ujjawal0503/iiitb_bc/
$ iverilog iiitb_bc.v iiitb_bc_tb.v
$ ./a.out
$ gtkwave iiitb_bc_out.vcd

The software used to run gate level synthesis is Yosys. Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the Yosys C++ code base

git clone https://github.com/YosysHQ/yosys.git
make
sudo make install make test

The commands to run synthesis in yosys are given below. First create an yosys script yosys_run.sh and paste the below commands.

read_liberty -lib lib/sky130_fd_sc_hd__tt_025C_1v80.lib
read_verilog iiitb_gc.v
synth -top iiitb_gc	
dfflibmap -liberty lib/sky130_fd_sc_hd__tt_025C_1v80.lib
abc -liberty lib/sky130_fd_sc_hd__tt_025C_1v80.lib
clean
flatten
write_verilog -noattr iiitb_bc_synth.v
stat
show

yosys -s yosys_run.sh

• Stats
  

• This is how layout is looking at first glance before proper placement
  

GLS stands for gate level simulation. When we write the RTL code, we test it by giving it some stimulus through the testbench and check it for the desired specifications. Similarly, we run the netlist as the design under test (dut) with the same testbench. Gate level simulation is done to verify the logical correctness of the design after synthesis. Also, it ensures the timing of the design. Commands to run the GLS are given below.

iverilog -DFUNCTIONAL -DUNIT_DELAY=#1 iiitb_bc_synth.v iiitb_bc_tb.v iiitb_bc/verilog_model/primitives.v /iiitb_bc/verilog_model/sky130_fd_sc_hd.v -iiitb_bc
./a.out
gtkwave iiitb_bc.vcd

Physical design is process of transforming netlist into layout which is manufacture-able [GDS]. Physical design process is often referred as PnR (Place and Route). Main steps in physical design are placement of all logical cells, clock tree synthesis & routing. During this process of physical design timing, power, design & technology constraints have to be met. Further design might require being optimized w.r.t power, performance and area.

Below are the stages and the respective tools that are called by openlane for the functionalities as described:

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, CU-GR, Klayout and a number of custom scripts for design exploration and optimization. The flow performs full ASIC implementation steps from RTL all the way down to GDSII.

more at https://github.com/The-OpenROAD-Project/OpenLane

$   apt install -y build-essential python3 python3-venv python3-pip

Docker installation process: https://docs.docker.com/engine/install/ubuntu/

$ sudo apt-get remove docker docker-engine docker.io containerd runc (removes older version of docker if installed)
$ sudo apt-get update
$ sudo apt-get install \
    ca-certificates \
    curl \
    gnupg \
    lsb-release    
$ sudo mkdir -p /etc/apt/keyrings
$ curl -fsSL https://download.docker.com/linux/ubuntu/gpg | sudo gpg --dearmor -o /etc/apt/keyrings/docker.gpg
$ echo \
  "deb [arch=$(dpkg --print-architecture) signed-by=/etc/apt/keyrings/docker.gpg] https://download.docker.com/linux/ubuntu \
  $(lsb_release -cs) stable" | sudo tee /etc/apt/sources.list.d/docker.list > /dev/null  
$ sudo apt-get update
$ sudo apt-get install docker-ce docker-ce-cli containerd.io docker-compose-plugin
$ apt-cache madison docker-ce (copy the version string you want to install)
$ sudo apt-get install docker-ce=<VERSION_STRING> docker-ce-cli=<VERSION_STRING> containerd.io docker-compose-plugin (paste the version string copies in place of <VERSION_STRING>)
$ sudo docker run hello-world (If the docker is successfully installed u will get a success message here)

goto home directory->

$   git clone https://github.com/The-OpenROAD-Project/OpenLane.git
$   cd OpenLane/
$   sudo make

To test the open lane

$ sudo make test

It takes approximate time of 5min to complete. After 43 steps, if it ended with saying Basic test passed then open lane installed succesfully.

Magic is a venerable VLSI layout tool, written in the 1980's at Berkeley by John Ousterhout, now famous primarily for writing the scripting interpreter language Tcl. Due largely in part to its liberal Berkeley open-source license, magic has remained popular with universities and small companies. The open-source license has allowed VLSI engineers with a bent toward programming to implement clever ideas and help magic stay abreast of fabrication technology. However, it is the well thought-out core algorithms which lend to magic the greatest part of its popularity. Magic is widely cited as being the easiest tool to use for circuit layout, even for people who ultimately rely on commercial tools for their product design flow.

More about magic at http://opencircuitdesign.com/magic/index.html

For Magic to be installed and work properly the following softwares have to be installed first: Run following commands one by one to fulfill the system requirement.

Installing csh

$ sudo apt-get install csh

Installing x11/xorg

$ sudo apt-get install x11

$ sudo apt-get install xorg

$ sudo apt-get install xorg openbox

Installing GCC

$ sudo apt-get install gcc

Installing build-essential

$ sudo apt-get install build-essential

Installing OpenGL

$ sudo apt-get install freeglut3-dev

Installing tcl/tk

$ sudo apt-get install tcl-dev tk-dev

To install magic goto home directory

$   git clone https://github.com/RTimothyEdwards/magic
$   cd magic/
$   ./configure
$   sudo make
$   sudo make install

type magic terminal to check whether it installed succesfully or not. type exit to exit magic.

Klayout Installation

$ sudo apt-get install klayout

The layout is generated using OpenLane. To run a custom design on openlane, Navigate to the openlane folder and run the following commands:

$ cd designs

$ mkdir iiitb_bc

$ cd iiitb_bc

$ mkdir src

$ touch config.json

$ cd src

$ touch iiitb_bc.v

The iiitb_bc.v file should contain the verilog RTL code you have used and got the post synthesis simulation for.

Copy sky130_fd_sc_hd__fast.lib, sky130_fd_sc_hd__slow.lib, sky130_fd_sc_hd__typical.lib and sky130_vsdinv.lef files to src folder in your design.

The final src folder should look like this:

The contents of the config.json are as follows. this can be modified specifically for your design as and when required.

As mentioned by kunal sir dont use defined DIE_AREA and FP_SIZING : absolute, use FP_SIZING : relative

{
    "DESIGN_NAME": "iiitb_bc",
    "VERILOG_FILES": "dir::src/iiitb_bc.v",
    "CLOCK_PORT": "clkin",
    "CLOCK_NET": "clkin",
    "GLB_RESIZER_TIMING_OPTIMIZATIONS": true,
    "CLOCK_PERIOD": 10,
    "PL_TARGET_DENSITY": 0.7,
    "FP_SIZING" : "relative",
    "pdk::sky130*": {
        "FP_CORE_UTIL": 30,
        "scl::sky130_fd_sc_hd": {
            "FP_CORE_UTIL": 20
        }
    },
    
    "LIB_SYNTH": "dir::src/sky130_fd_sc_hd__typical.lib",
    "LIB_FASTEST": "dir::src/sky130_fd_sc_hd__fast.lib",
    "LIB_SLOWEST": "dir::src/sky130_fd_sc_hd__slow.lib",
    "LIB_TYPICAL": "dir::src/sky130_fd_sc_hd__typical.lib",  
    "TEST_EXTERNAL_GLOB": "dir::../iiitb_bc/src/*"


}

Save all the changes made above and Navigate to the openlane folder in terminal and give the following command :
1. Running openlane in interactive mode: The commands to the run the flow in interactive mode is given below:

$ make mount (if this command doesnot go through prefix it with sudo)

After entering the openlane container give the following command:

$ ./flow.tcl -interactive

This command will take you into the tcl console. In the tcl console type the following commands:

 % package require openlane 0.9

2. Preparing the design and including the lef files: The commands to prepare the design and the reports and results along with the command to include the lef files is given below:

% prep -design iiitb_bc

The following commands are to merge external the lef files to the merged.nom.lef. In our case sky130_vsdiat is getting merged to the lef file

set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs

1. The command to run the synthesis is run_synthesis.This runs the synthesis where yosys translates RTL into circuit using generic components and abc maps the circuit to Standard Cells.

%  run_synthesis

2. The synthesized netlist is present in the results folder and the stats are present in the reports folder

3. Calcuation of Flop Ratio:

Flop ratio = Number of D Flip flops 
             ______________________
             Total Number of cells 

To run the Floorplan use the command:

% run_floorplan

Navigate to results->floorplan and type the Magic command in terminal to open the floorplan

$ magic -T /home/ujjawal/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read ../../tmp/merged.nom.lef def read iiitb_bc.def &

Die Area post floorplan:

Core Area post floorplan:

To run the Placement use the command:

% run_placement

Navigate to results->placement and type the Magic command in terminal to open the placement view

$ magic -T /home/ujjawal/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read ../../tmp/merged.max.lef def read iiitb_bc.def &

Area report post placement_resizing:

To run CTS use the below command:

% run_cts

% run_routing

Navigate to results->routing and type the Magic command in terminal to open the routing view

$ magic -T /home/ujjawal/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read ../../tmp/merged.nom.lef def read iiitb_bc.def &

Routing View

We can also run the whole flow at once instead of step by step process by giving the following command in openlane container

$ ./flow.tcl -design iiitb_4bbc

All the steps will be automated and all the files will be generated.

Total Gate Count = 24

Area = 7008um^2

Perfomance = 1/(65-51.26) =72.78MHz

Flop Ratio = 4/24 =.16

Internal power = .659 uW (53.2%)
Switching power = .579 uW (46.8%)
Leakage Power = .271 nW (0.0%)
Total Power = 1.24 uW (100 %)

• Ujjawal Sharma
• Kunal Ghosh

• Kunal Ghosh, Director, VSD Corp. Pvt. Ltd.

• Ujjawal sharma, Postgraduate Student, International Institute of Information Technology, Bangalore ujjawal0503@gmail.com
• Kunal Ghosh, Director, VSD Corp. Pvt. Ltd. kunalghosh@gmail.com

1.> https://verilogcodes.blogspot.com/2015/10/verilog-code-for-updown-counter-using.html
2.> https://www.electronics-tutorials.ws/counter/count_4.html#:~:text=Bidirectional%20counters%2C%20also%20known%20as,control%20input%20as%20shown